Daniel P Leak

US Patent:

6901456, May 31, 2005

Filed:

Jun 18, 1999

Appl. No.:

09/336649

Inventors:

Daniel Leak - Wichita KS, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F013/00

US Classification:

710 9, 710 2, 710 3, 710 8, 710300

Abstract:

A method and system for selectively interconnecting two SCSI host buses where each SCSI host bus includes a host device and multiple addressable SCSI target devices, each SCSI target device having a multibit SCSI ID associated therewith. A SCSI cross-link repeater is interposed between the two SCSI host buses and selectively enabled. Each time the SCSI cross-link repeater is enabled, the repeater enable signal is utilized to automatically alter the most significant bit of the multibit SCSI ID associated with each SCSI target device on the second SCSI host bus, such that those SCSI target devices do not duplicate the SCSI IDs of the SCSI target devices on the first SCSI host bus. Disabling the SCSI cross-link repeater automatically resets the most significant bit of the multibit SCSI IDs, restoring the original SCSI IDs for those devices.

US Patent:

53751272, Dec 20, 1994

Filed:

Mar 25, 1992

Appl. No.:

7/856613

Inventors:

Daniel P. Leak - Wichita KS
John R. Kloeppner - Wichita KS

Assignee:

NCR Corporation - Dayton OH

International Classification:

H03M 1300
G06F 1100

US Classification:

371 401

Abstract:

An error correction code (ECC) generator/checker for processing high bandwidth data block transfers. The high bandwidth ECC generator/checker logic includes a plurality stages, each stage including Reed-Solomon Cyclic Redundancy Check (RS CRC) code logic for processing a single data word. The stages can be configured to operate in parallel to process multiple-word parallel, high bandwidth transfers, or individually wherein each stage processes data in a word-serial manner. Each stage includes a first input for receiving a respective word portion of a multiple-word transfer, a second input for receiving either an intermediate ECC value from a previous stage or a feed back value, means for combining data words received at the first and second inputs, an alpha multiplier and an output for providing an ECC word. When configured to operate in high bandwidth mode the output of the stages are connected in series such that the first stage output is connected to the second input of the second stage, the second stage output is connected to the second input of the third stage, and so on. The output of the final stage is fed back to the second input of the first stage.