Christopher D Abel

US Patent:

6518906, Feb 11, 2003

Filed:

Jul 16, 2001

Appl. No.:

09/906162

Inventors:

Christopher J Abel - Coplay PA
Joseph Anidjar - Asbury NJ
Peicheng Ju - Berkeley Heights NJ

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H03M 166

US Classification:

341144, 341119, 236115

Abstract:

The performance of a single-bit cell in a DAC is improved by decoupling the voltage swing across the load resistors from the output of the current steering device. This can be achieved by providing for a single-bit cell having a first load resistor R and a second load resistor R a current steering circuit, and a decoupling circuit operably coupled between the current steering circuit and the resistors R R The current steering circuit steers at least part of a current I through a circuit path towards either the first resistor R or the second resistor R The decoupling circuit decouples voltage swings across the load resistors R R from the current steering circuit.

US Patent:

6668334, Dec 23, 2003

Filed:

Jun 27, 2000

Appl. No.:

09/604842

Inventors:

Christopher John Abel - Whitehall PA
Angelo Rocco Mastrocola - West Lawn PA
Douglas Edward Sherry - Mertztown PA
William Burdett Wilson - Macungie PA

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G06F 104

US Classification:

713500, 713502, 327 20

Abstract:

A loss-of-clock (LOC) detector circuit detects a clock failure substantially within a specified number of clock periods and generates a loss-of-clock signal. The LOC detector includes a frequency-to-current converter which generates a charging current substantially proportional to a frequency of an input clock. A capacitor accepts the charging current and provides a terminal voltage that changes in response to the charging current. An edge detector receives the input clock signal as an input and produces an output pulse on an edge of the input clock signal. A switch is coupled to the capacitor such that the capacitor is discharged to a reference potential when the switch is closed. The switch is controlled by the edge detector to close when the edge detector output pulse is asserted. A comparator generates a loss-of-clock signal when the voltage on the capacitor passes a trip voltage of the comparator.

US Patent:

7116178, Oct 3, 2006

Filed:

Mar 3, 2005

Appl. No.:

11/071707

Inventors:

Christopher J. Abel - Coplay PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03L 7/08
H03L 7/099

US Classification:

331 17, 331 34, 331177 R

Abstract:

Embodiments of the invention include a voltage-controlled oscillator (VCO) circuit in which the gain of the VCO is proportional to the output or operating frequency of the VCO. The VCO circuit includes a voltage-controlled oscillator, a current scaling block, and a summing node. The summing node couples a VCO control current and a VCO reference current into the current scaling block. The current scaling block scales the sum of the currents by a scaling factor. The output of the current scaling block, which is coupled to the input of the VCO, provides a bias current to the VCO, which bias current adjusts the oscillation frequency of the oscillator. The VCO control current and the VCO reference current are scaled by the same scaling factor, thus allowing the gain of the VCO to be proportional to but not dependent on the output frequency of the VCO.

US Patent:

7208998, Apr 24, 2007

Filed:

Apr 12, 2005

Appl. No.:

11/103813

Inventors:

Christopher J. Abel - Coplay PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G05F 1/10
G05F 3/02

US Classification:

327538, 327543, 323315, 330288

Abstract:

A bias circuit for providing at least first and second bias signals for biasing a cascode current source and/or a cascode current sink includes a resistive element and first, second and third transistors, each transistor having first and second source/drain terminals and a gate terminal. The first source/drain terminal of the first transistor is coupled to the gate terminal, the first bias signal being generated at the first source/drain terminal in response to receiving a first reference current at the first source/drain terminal. A first end of the first resistive element is coupled to the second source/drain terminal of the first transistor. The gate terminal of the second transistor is coupled to the gate terminal of the first transistor, the second bias signal being generated at the first source/drain terminal of the second transistor in response to receiving a second reference current at the first source/drain terminal of the second transistor. The first source/drain terminal of the third transistor is coupled to the second source/drain terminal of the second transistor, the second source/drain terminal of the third transistor is coupled to a second end of the first resistive element, and the gate terminal of the third transistor is coupled to the first source/drain terminal of the second transistor.

US Patent:

7236037, Jun 26, 2007

Filed:

May 26, 2005

Appl. No.:

11/138777

Inventors:

Christopher J. Abel - Coplay PA, US
Vladimir Sindalovsky - Perkasie PA, US
Craig B. Ziemer - Fleetwood PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03K 3/00

US Classification:

327291, 327298

Abstract:

A delay loop (e. g. , a voltage-controlled delay loop) has (at least) two devices (e. g. , interpolators) for generating clock signals for injection into the delay elements of the delay loop in a leap-frog manner, in which, while one interpolator is generating the clock signal currently selected for injection, the other interpolator can be controlled to generate the next clock signal to be selected for injection. This leap-frog technique can provide more settling time for generating injected clock signals than implementations that rely on a single interpolator.

US Patent:

7312663, Dec 25, 2007

Filed:

Jun 16, 2005

Appl. No.:

11/154314

Inventors:

Christopher J. Abel - Coplay PA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03L 7/00

US Classification:

331 16, 331 17, 331 34, 331177 R, 327156

Abstract:

An integrated circuit includes a phase-locked loop (PLL) in which the loop bandwidth of the PLL is proportional to the input frequency of the PLL. The PLL includes a phase/frequency detector (PFD), a charge pump, a loop filter, and a voltage-controlled oscillator (VCO) that generates the PLL output clock. The VCO includes a current scaling block that scales the sum of a variable current, which is proportional to the loop filter voltage, and a fixed current. The frequency of the PLL output clock is a function of the current output from the current scaling block. Since the same scaling factor is applied to both the fixed current and the variable current, the gain from the loop filter voltage to the PLL output frequency is proportional to the PLL output frequency, and thus the loop bandwidth of the PLL is proportional to the PLL input frequency.

US Patent:

7330060, Feb 12, 2008

Filed:

Sep 7, 2005

Appl. No.:

11/221387

Inventors:

Christopher J. Abel - Coplay PA, US
Abhishek Duggal - Allentown PA, US
Peter C. Metz - Macungie PA, US
Vladimir Sindalovsky - Perkasie PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03L 7/06

US Classification:

327158, 327161, 327163

Abstract:

Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is generated if a clock signal has a time lag relative to a reference signal. The first and second values are accumulated to generate an N bit digital word; and the N bit digital word is reduced to an M bit digital word, where M is less than N. Thereafter, the M bit digital word can be converted to an analog bias signal. The reducing step can be performed, for example, by a sigma-delta modulator. The high frequency quantization noise generated by the sigma-delta modulator can be filtered using a low pass filter. The converting step can be performed by a digital-to-analog converter, such as a master/slave digital-to-analog converter.

US Patent:

7352313, Apr 1, 2008

Filed:

May 31, 2005

Appl. No.:

11/141498

Inventors:

Christopher J. Abel - Coplay PA, US
Peter C. Metz - Macungie PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03M 1/66

US Classification:

341145, 341144

Abstract:

Methods and apparatus are provided for improved digital-to-analog conversion. The disclosed digital-to-analog converter comprises a master digital-to-analog converter that generates a master analog value, and a slave digital-to-analog converter that generates a slave analog value that is based on the master analog value. The slave analog value can be, for example, substantially proportional to the master analog value. The master D/A converter can be varied during a coarse tuning mode, while the input to the slave D/A can be fixed, for example, to an approximately mid-range value until the master analog value satisfies one or more predefined conditions. Thereafter, during a fine tuning mode, the slave D/A converter can be varied, while the master D/A converter is fixed, so that the output Y is equal to a desired value (within a specified tolerance).

Author:

Christopher Abel

ISBN #:

0312749597

Author:

Christopher Abel

ISBN #:

0485177137

Author:

Christopher Abel

ISBN #:

0822306794

Address:

5227 Lincolnshire Ct, Dallas, TX 75287

VIN:

4T1BK36B77U223213

Make:

TOYOTA

Model:

AVALON

Year:

2007