Brian S Cruikshank

US Patent:

6829315, Dec 7, 2004

Filed:

Jan 19, 2000

Appl. No.:

09/487139

Inventors:

Brian S. Cruikshank - Boulder CO

Assignee:

Mindspeed Technologies, Inc. - Newport Beach CA

International Classification:

H04L 700

US Classification:

375354, 375364, 375371, 370503, 370506, 341 50, 341102

Abstract:

A data communication circuit includes a decoder and an alignment buffer. The decoder receives and decodes parallel (N) bit channels into parallel (M+X) bit channels with signaling bits that indicate headers in the parallel (M+X) bit channels. The decoder transfers the parallel (M+X) bit channels to the alignment buffer. The alignment buffer recovers and aligns parallel (M) bit channels using the signaling bits. The alignment buffer generates a clock selection signal using the signaling bits. The alignment buffer transfers the aligned parallel (M) bit channels and the clock selection signal. The alignment buffer can have a length that is a multiple of a frame length for the (M) bit parallel channels.