Francis P Cruise

US Patent:

7463869, Dec 9, 2008

Filed:

Apr 26, 2005

Appl. No.:

11/115815

Inventors:

Chih-Ming Hung - McKinney TX, US
Francis P. Cruise - Dallas TX, US
Dirk Leipold - Plano TX, US
Robert B. Staszewski - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04B 1/04

US Classification:

4551272, 4551803, 4552401, 455260, 375308, 375297

Abstract:

A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.

US Patent:

7983375, Jul 19, 2011

Filed:

Jan 28, 2008

Appl. No.:

12/021205

Inventors:

Fikret Dulger - Plano TX, US
Robert B. Staszewski - Garland TX, US
Francis P. Cruise - Dallas TX, US
Gennady Feygin - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03D 3/24

US Classification:

375376

Abstract:

A novel and useful variable delay digitally controlled crystal oscillator (DCXO) buffer (i. e. slicer). A conventional slicer following the DCXO is modified to introduce a controlled random variable delay into the buffered DCXO clock. The resultant output clock signal is then used as input to the TDC of an ADPLL circuit to alleviate the subharmonic mixing based deterioration caused by LO/TX coupling through the crystal pins, and to alleviate the dead-beat effects caused by the finite resolution of the TDC. Two mechanisms for introducing variable delay into the buffered DCXO output clock signal are presented: a first mechanism that creates variable delay in fine steps and a second mechanism that creates variable delay in coarse steps. In both mechanisms, switches are incorporated into the slicer circuitry and controlled using digital bit sequences which may comprise dithering signals. The switches are turned on and off via the digital bit sequences which varies the delay of the slicer clock output which serves to shift the rising and falling transition points of the resultant output clock signal.

US Patent:

20060291589, Dec 28, 2006

Filed:

Aug 11, 2005

Appl. No.:

11/203504

Inventors:

Oren Eliezer - Plano TX, US
Francis Cruise - Dallas TX, US
Robert Staszewski - Garland TX, US
Jaimin Mehta - Richardson TX, US

International Classification:

H04L 27/12

US Classification:

375302000

Abstract:

A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, θ). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.

US Patent:

20190097316, Mar 28, 2019

Filed:

Sep 26, 2017

Appl. No.:

15/716095

Inventors:

- San Jose CA, US
Francis Patrick Cruise - San Jose CA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H01Q 3/22
G01R 27/26
H01Q 5/30

Abstract:

A computing device includes a processing device that adjusts the operating parameters of one or more antennas based on capacitances detected at the one or more antennas. Capacitance sensors measure the capacitances detected at the one or more antennas and generate capacitance data. The processing device may adjust operating parameters of one or more antennas, such as frequency/band, radiation pattern, power, angle diversity, space diversity, etc., based on the capacitance data.