Bradford B Congdon from 22757 NW Fisher Rd, Banks, OR 97109, age 65

Us Patents

Network Management Card For Use In A System For Screen Image Capturing
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US Patent:

6556208, Apr 29, 2003
Filed:

Mar 23, 1999
Appl. No.:

09/274913
Inventors:

Bradford B. Congdon - Olympia WA
Rama U. Reddy - Beaverton OR
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 1314
US Classification:

345520, 710107, 710260
Abstract:

A network management card is provided to capture a screen image of a host system for transmission over a computer network for remote viewing and remote system management. The network management card is provided with a processor which processes a program to implement a video capture sequence of operations; and a bus controller having operations controlled by the processor, which tracks events on a bus of the host system, including operations of a video subsystem of the host system, and which executes a video capture sequence of operations to capture a screen image provided by the video subsystem of the host system for transmission to a remote system over a computer network or other communications link for remote viewing and remote system management.

Distributed Read And Write Caching Implementation For Optimized Input/Output Applications
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US Patent:

6681292, Jan 20, 2004
Filed:

Aug 27, 2001
Appl. No.:

09/940835
Inventors:

Kenneth C. Creta - Gig Harbor WA
Mike Bell - Beaverton OR
Robert George - Austin TX
Bradford B Congdon - Olympia WA
Robert Blankenship - Tacoma WA
Duane January - Beaverton OR
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 1300
US Classification:

711119, 711141, 711145, 711146, 709217
Abstract:

A caching input/output hub includes a host interface to connect with a host. At least one input/output interface is provided to connect with an input/output device. A write cache manages memory writes initiated by the input/output device. At least one read cache, separate from the write cache, provides a low-latency copy of data that is most likely to be used. The at least one read cache is in communication with the write cache. A cache directory is also provided to track cache lines in the write cache and the at least one read cache. The cache directory is in communication with the write cache and the at least one read cache.

Mechanism For Preserving Producer-Consumer Ordering Across An Unordered Interface
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US Patent:

6801976, Oct 5, 2004
Filed:

Aug 27, 2001
Appl. No.:

09/940292
Inventors:

Kenneth C. Creta - Gig Harbor WA
Bradford B. Congdon - Olympia WA
Tony S Rand - Tacoma WA
Deepak Ramachandran - Tacoma WA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 1300
US Classification:

710310, 710 39, 710313
Abstract:

An input/output hub includes an inbound ordering queue (IOQ) to receive inbound transactions. All read and write transactions have a transaction completion. Peer-to-peer transactions are not permitted to reach a destination until after all prior writes in the IOQ have been completed. A write in a peer-to-peer transaction does not permit subsequent accesses to proceed until the write is guaranteed to be in an ordered domain of the destination. An IOQ read bypass buffer is provided to receive read transactions pushed from the IOQ to permit posted writes and read/write completions to progress through the IOQ. An outbound ordering queue (OOQ) stores outbound transactions and completions of the inbound transactions. The OOQ also issues write completions for posted writes. An OOQ read bypass buffer is provided to receive read transactions pushed from the OOQ to permit posted writes and read/write completions to progress through the OOQ.

Reordering Unrelated Transactions From An Ordered Interface
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US Patent:

7162546, Jan 9, 2007
Filed:

Dec 27, 2001
Appl. No.:

10/034641
Inventors:

Kenneth C. Creta - Gig Harbor WA, US
Robert T. George - Austin TX, US
Bradford B. Congdon - Olympia WA, US
Tony S. Rand - Tacoma WA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 3/00
US Classification:

710 5, 710 6, 710 7, 710 33, 710 36
Abstract:

A computer chipset having an identifier module and a router. The identifier module is configured to add sequence identifiers to each transaction in independent ordered sequences of transactions. The sequence identifiers identify which ordered sequence the transactions belong to. The identifier module combines the ordered sequences of transactions into a combined ordered sequence of transactions. The combined ordered sequence of transactions are sent over an ordered interface. A router then separates the combined ordered sequence of transactions into ordered queues based on the sequence identifiers associated with the transactions. The transactions in the ordered queues are executed in an order that reduces the time required to complete the transactions.

Network Management Card For Use In A System For Screen Image Capturing
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US Patent:

7429990, Sep 30, 2008
Filed:

Feb 21, 2003
Appl. No.:

10/369727
Inventors:

Bradford B. Congdon - Olympia WA, US
Rama U. Reddy - Beaverton OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G09G 5/39
G09G 5/36
G06F 13/00
G06F 13/14
US Classification:

345520, 345531, 345545, 710107
Abstract:

A network management card is provided to capture a screen image of a host system for transmission over a computer network for remote viewing and remote system management. The network management card is provided with a processor which processes a program to implement a video capture sequence of operations; and a bus controller having operations controlled by the processor, which tracks events on a bus of the host system, including operations of a video subsystem of the host system, and which executes a video capture sequence of operations to capture a screen image provided by the video subsystem of the host system for transmission to a remote system over a computer network or other communications link for remote viewing and remote system management.

Cache Usage For Concurrent Multiple Streams
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US Patent:

20040022094, Feb 5, 2004
Filed:

Feb 5, 2003
Appl. No.:

10/358618
Inventors:

Sivakumar Radhakrishnan - Portland OR, US
Chitra Natarajan - Flushing NY, US
Kenneth Creta - Gig Harbor WA, US
Bradford Congdon - Olympia WA, US
Hui Lu - San Jose CA, US
International Classification:

G11C007/00
US Classification:

365/200000
Abstract:

In a system supporting concurrent multiple streams that pass through a cache between memory and the requesting devices, various techniques improve the efficient use of the cache. Some embodiments use adaptive pre-fetching of memory data using a dynamic table to determine the maximum number of pre-fetched cache lines permissible per stream. Other embodiments dynamically allocate the cache to the active streams. Still other embodiments use a programmable timer to deallocate inactive streams.

Method And Apparatus For Reducing Bus Bridge Thrashing By Temporarily Masking Agent Requests To Allow Conflicting Requests To Be Completed
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US Patent:

62928651, Sep 18, 2001
Filed:

Jun 23, 1998
Appl. No.:

9/103622
Inventors:

Michael J. McTague - Portland OR
Bradford B. Congdon - Aloha OR
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 1338
US Classification:

710262
Abstract:

A method and apparatus for masking processor requests to improve bus efficiency includes a bus bridge having a detection logic for determining when a first processor on a first bus has been backed off the first bus a predetermined number of times. When the detection logic determines the first processor has been backed off the first bus the predetermined number of times, a timer is set to a first value, with the first value being sufficient to allow an agent on a second bus to access the first bus. A masking logic, coupled to the detection logic and the timer, is for masking requests from the first processor until the timer expires.

Method And Apparatus For Reducing Bus Bridge Thrashing By Temporarily Masking Agent Requests To Allow Conflicting Requests To Be Completed
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US Patent:

58505571, Dec 15, 1998
Filed:

May 10, 1996
Appl. No.:

8/644833
Inventors:

Michael J. McTague - Portland OR
Bradford B. Congdon - Aloha OR
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 1338
US Classification:

395735
Abstract:

A method and apparatus for masking processor requests to improve bus efficiency includes a bus bridge having a detection logic for determining when a first processor on a first bus has been backed off the first bus a predetermined number of times. When the detection logic determines the first processor has been backed off the first bus the predetermined number of times, a timer is set to a first value, with the first value being sufficient to allow an agent on a second bus to access the first bus. A masking logic, coupled to the detection logic and the timer, is for masking requests from the first processor until the timer expires.