Bin Yu

Author:

Bin Yu

ISBN #:

0700610952

US Patent:

6339017, Jan 15, 2002

Filed:

Jun 20, 2000

Appl. No.:

09/596993

Inventors:

Bin Yu - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438585, 438584, 438197, 438595

Abstract:

A method of manufacturing small structures or narrow structures on an ultra-large scale integrated circuit utilizes a hard mask. A mask layer can be deposited over a top surface of a material above a semiconductor substrate. A mask layer can be lithographically patterned to have a feature. The side walls of the feature can be oxidized. The oxidized side walls can be removed to reduce the size of the feature below one lithographic feature. The material underneath mask layer can be etched in accordance with the feature without the oxidized side walls.

US Patent:

6342410, Jan 29, 2002

Filed:

Jul 10, 2000

Appl. No.:

09/612781

Inventors:

Bin Yu - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2184

US Classification:

438164

Abstract:

For fabricating a field effect transistor, a semiconductor pillar is formed on a layer of insulating material with a top surface and first and second side surfaces of the semiconductor pillar being exposed. A layer of dielectric material is formed on the top surface and the first and second side surfaces of the semiconductor pillar. A layer of conductive material is deposited on the layer of dielectric material on the top surface and the first and second side surfaces of the semiconductor pillar. A dummy dielectric structure is formed that covers a portion of the layer of conductive material such that a remaining portion of the layer of conductive material on the semiconductor pillar is exposed. The dummy dielectric structure has a predetermined sidewall on the layer of conductive material on the semiconductor pillar. A layer of hardmask dielectric is deposited on top and on the predetermined sidewall of the dummy dielectric structure and on the remaining portion of the layer of conductive material that is exposed.

US Patent:

6342438, Jan 29, 2002

Filed:

Nov 6, 1998

Appl. No.:

09/187379

Inventors:

Bin Yu - Fremont CA
Ming-Ren Lin - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21265

US Classification:

438520, 438528, 438546

Abstract:

A dual doped CMOS gate structure utilizes a nitrogen implant to suppress dopant inter-diffusion. The nitrogen implant is provided above standard trench isolation structures. Alternatively, an oxygen implant can be utilized. The use of the implant allows an increase in packing density for ultra-large-scale integrated (ULSI) circuits. The doping for N-channel and P-channel active regions can be completed when the polysilicon gate structures are doped.

US Patent:

6348387, Feb 19, 2002

Filed:

Jul 10, 2000

Appl. No.:

09/612771

Inventors:

Bin Yu - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438303, 257389

Abstract:

For fabricating a field effect transistor within an active device area of a semiconductor substrate, a gate dielectric is formed on the active device area of the semiconductor substrate, and a gate structure is formed on the gate dielectric with the gate structure being comprised of a first conductive material. A drain spacer comprised of a second conductive material is formed on a first sidewall of the gate structure, and a first liner dielectric is formed between the drain spacer and the first sidewall of the gate structure and between the drain spacer and the semiconductor substrate. A source spacer comprised of the second conductive material is formed on a second sidewall of the gate structure, and a second liner dielectric is formed between the source spacer and the second sidewall of the gate structure and between the source spacer and the semiconductor substrate. Application of at least a drain threshold voltage on the drain spacer with respect to the semiconductor substrate induces charge accumulation in the semiconductor substrate under the first liner dielectric to form a drain extension of the field effect transistor. Similarly, application of at least a source threshold voltage on the source spacer with respect to the semiconductor substrate induces charge accumulation in the semiconductor substrate under the second liner dielectric to form a source extension of the field effect transistor.

US Patent:

6355543, Mar 12, 2002

Filed:

Sep 29, 1998

Appl. No.:

09/162919

Inventors:

Bin Yu - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438535, 438303, 438308, 438528

Abstract:

A method for making a ULSI MOSFET chip includes forming a transistor gate on a substrate and defining the contours of shallow source/drain extensions by implanting a first pre-amorphization (PAI) substance into the substrate. A sidewall spacer is then formed on the substrate next to the gate, and a second PAI substance is implanted into the substrate to defame the contours of a deep source/drain junction. Then, a dopant is provided on the surface of the substrate, and the portions of the substrate that contain PAI substances are silicidized to render the portions relatively more absorbing of laser energy. These pre-amorphized portions are then annealed by laser to melt only the pre-amorphized portions. During melting, the dopant is driven from the surface of the substrate into the pre-amorphized portions to thereby establish source/drain regions below the gate.

US Patent:

6361874, Mar 26, 2002

Filed:

Jun 20, 2000

Appl. No.:

09/597623

Inventors:

Bin Yu - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

428514, 438527, 438299, 438301, 438303, 438307

Abstract:

A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region 300 nm thick. The shallow amorphous region can be between 10-15 nm below the top surface of the substrate, and the deep amorphous region can be between 150-200 nm below the top surface of the substrate. The process can reduce gate over-melting effects. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs).

US Patent:

6362055, Mar 26, 2002

Filed:

Aug 31, 1998

Appl. No.:

09/144527

Inventors:

Ming-Ren Lin - Cupertino CA
Bin Yu - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 218234

US Classification:

438275, 438527, 438529, 438283

Abstract:

A semiconductor device includes a first gate stack and a second gate stack, each gate stack corresponding to a gate of a FET formed on the semiconductor device. The first gate stack includes a gate material formed from one of poly-silicon, poly-SiGe, and amorphous silicon. The gate material is implanted with a dopant of a first conductivity type at a first concentration. A metal silicide layer is formed over the doped gate material. The second gate stack includes a gate material formed from one of poly-silicon, poly-SiâGe, and amorphous silicon. The gate material of the second gate stack is implanted with a dopant of a second conductivity type at a second concentration.

US Patent:

6365445, Apr 2, 2002

Filed:

May 1, 2001

Appl. No.:

09/846957

Inventors:

Bin Yu - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2184

US Classification:

438149, 438151, 438163, 438164, 257347, 257353

Abstract:

For fabricating a field effect transistor on a buried insulating material in SOI (semiconductor on insulator) technology, a dielectric island is formed on the buried insulating material. An opening is etched through the buried insulating material at a location away from the dielectric island. An amorphous semiconductor material is deposited to fill the opening through the buried insulating material and to surround the dielectric island. The amorphous semiconductor material is polished until the top surface of the dielectric island is exposed and such that the amorphous semiconductor material surrounds the dielectric island. A layer of the amorphous semiconductor material is deposited on top of the dielectric island and on top of the amorphous semiconductor material surrounding the dielectric island. The amorphous semiconductor material surrounding the dielectric island and the layer of the amorphous semiconductor material are recrystallized to form a substantially single crystal structure of semiconductor material. A gate dielectric and a gate electrode of the field effect transistor are formed on top of a thinner portion of the semiconductor material disposed on the dielectric island.