Arvind G Mithal

US Patent:

6597664, Jul 22, 2003

Filed:

Aug 19, 1999

Appl. No.:

09/377372

Inventors:

Arvind Mithal - Arlington MA
James C. Hoe - Cambridge MA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

H04L 1266

US Classification:

370252, 370463, 370503

Abstract:

A method for specifying and synthesizing a synchronous digital circuit by first accepting a specification of an asynchronous system in which stored values are updated according to a set of state transition rules. For instance, the state transition rules are specified as a Term Rewriting System (TRS) in which each rule specifies a number of allowable state transitions, and includes a logical precondition on the stored values and a functional specification of the stored values after a state transition in terms of the stored values prior to the state transition. The specification of the asynchronous circuit is converted into a specification of an synchronous circuit in which a number of state transitions can occur during each clock period. The method includes identifying sets of state transitions, for example by identifying sets of TRS rules, that can occur during a single clocking period and forming the specification of the synchronous circuit to allow any of the state transitions in a single set to occur during any particular clocking period.

US Patent:

6636950, Oct 21, 2003

Filed:

Apr 27, 1999

Appl. No.:

09/300641

Inventors:

Arvind Mithal - Arlington MA
Xiaowei Shen - Cambridge MA
Lawrence Rogel - Brookline MA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

G06F 1200

US Classification:

711147, 711117, 711141, 711143

Abstract:

A computer architecture that includes a hierarchical memory system and one or more processors. The processors execute memory access instructions whose semantics are defined in terms of the hierarchical structure of the memory system. That is, rather than attempting to maintain the illusion that the memory system is shared by all processors such that changes made by one processor are immediately visible to other processors, the memory access instructions explicitly address access to a processor-specific memory, and data transfer between the processor-specific memory and the shared memory system. Various alternative embodiments of the memory system are compatible with these instructions. These alternative embodiments do not change the semantic meaning of a computer program which uses the memory access instructions, but allow different approaches to how and when data is actually passed from one processor to another.

US Patent:

6757787, Jun 29, 2004

Filed:

Dec 19, 2002

Appl. No.:

10/325028

Inventors:

Xiaowei Shen - Cambridge MA
Arvind Mithal - Arlington MA
Lawrence Rogel - Brookline MA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

G06F 1200

US Classification:

711141, 711147, 711118, 711148, 709215

Abstract:

A methodology for designing a distributed shared-memory system, which can incorporate adaptation or selection of cache protocols during operation, guarantees semantically correct processing of memory instructions by the multiple processors. A set of rules includes a first subset of âmandatoryâ rules and a second subset of âvoluntaryâ rules such that correct operation of the memory system is provided by application of all of the mandatory rules and selective application of the voluntary rules. A policy for enabling voluntary rules specifies a particular coherent cache protocol. The policy can include various types of adaptation and selection of different operating modes for different addresses and at different caches. A particular coherent cache protocol can make use of a limited capacity directory in which some but not necessarily all caches that hold a particular address are identified in the directory. In another coherent cache protocol, various caches hold an address in different modes which, for example, affect communication between a cache and a shared memory in processing particular memory instructions.

US Patent:

6901055, May 31, 2005

Filed:

Aug 18, 2000

Appl. No.:

09/641997

Inventors:

James C. Hoe - Pittsburgh PA, US
Arvind Mithal - Arlington MA, US

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

H04L012/66

US Classification:

370252, 370466, 370503

Abstract:

A method for specifying and synthesizing a synchronous digital circuit by first accepting a specification of an asynchronous system in which stored values are updated according to a set of state transition rules. For instance, the state transition rules are specified as a Term Rewriting System (TRS) in which each rule specifies a number of allowable state transitions, and includes a logical precondition on the stored values and a functional specification of the stored values after a state transition in terms of the stored values prior to the state transition. The specification of the asynchronous circuit is converted into a specification of a synchronous circuit in which a number of state transitions can occur during each clock period. The method includes identifying sets of state transitions, for example by identifying sets of TRS rules, that can occur during a single clocking period and forming the specification of the synchronous circuit to allow any of the state transitions in a single set to occur during any particular clocking period.

US Patent:

6977907, Dec 20, 2005

Filed:

Jul 22, 2003

Appl. No.:

10/624962

Inventors:

Arvind Mithal - Arlington MA, US
James C. Hoe - Cambridge MA, US

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

G06F017/50

US Classification:

370252, 370463, 716 18

Abstract:

A method for specifying and synthesizing a synchronous digital circuit by first accepting a specification of an asynchronous system in which stored values are updated according to a set of state transition rules. For instance, the state transition rules are specified as a Term Rewriting System (TRS) in which each rule specifies a number of allowable state transitions, and includes a logical precondition on the stored values and a functional specification of the stored values after a state transition in terms of the stored values prior to the state transition. The specification of the asynchronous circuit is converted into a specification of an synchronous circuit in which a number of state transitions can occur during each clock period. The method includes identifying sets of state transitions, for example by identifying sets of TRS rules, that can occur during a single clocking period and forming the specification of the synchronous circuit to allow any of the state transitions in a single set to occur during any particular clocking period.

US Patent:

7392352, Jun 24, 2008

Filed:

Jul 7, 2005

Appl. No.:

11/176518

Inventors:

Arvind Mithal - Arlington MA, US
Xiaowei Shen - Cambridge MA, US
Lawrence Rogel - Brookline MA, US

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

G06F 12/00

US Classification:

711147, 711117, 711141, 711143

Abstract:

A computer architecture that includes a hierarchical memory system and one or more processors. The processors execute memory access instructions whose semantics are defined in terms of the hierarchical structure of the memory system. That is, rather than attempting to maintain the illusion that the memory system is shared by all processors such that changes made by one processor are immediately visible to other processors, the memory access instructions explicitly address access to a processor-specific memory, and data transfer between the processor-specific memory and the shared memory system. Various alternative embodiments of the memory system are compatible with these instructions. These alternative embodiments do not change the semantic meaning of a computer program which uses the memory access instructions, but allow different approaches to how and when data is actually passed from one processor to another.

US Patent:

7716608, May 11, 2010

Filed:

Jun 1, 2006

Appl. No.:

11/421612

Inventors:

Arvind Mithal - Arlington MA, US
Daniel L. Rosenband - San Mateo CA, US

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

G06F 17/50

US Classification:

716 1

Abstract:

A scheduling approach enables scheduling sequential execution of rules in a single cycle of a synchronous system without necessarily requiring explicit implementation of a composite rule for each sequence of rules than may be composed. One method for designing a synchronous digital system includes using modules with multiple successive interfaces such that within the a single clocked cycle, each module performs a function equivalent to completing interactions through one of its interfaces before performing interactions through any succeeding one of its interfaces. The scheduled state transition rules are associated with corresponding interfaces of the modules.

US Patent:

7724760, May 25, 2010

Filed:

Aug 12, 2003

Appl. No.:

10/639269

Inventors:

Hari Balakrishnan - Winchester MA, US
Srinivas Devadas - Lexington MA, US
Arvind Mithal - Arlington MA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 12/56

US Classification:

370416, 3702301, 370414

Abstract:

A method for selecting a queue for service across a shared link. The method includes classifying each queue from a group of queues within a plurality of ingresses into one tier of a number “N” of tiers. The number “N” is greater than or equal to 2. Information about allocated bandwidth is used to classify at least some of the queues into the tiers. Each tier is assigned a different priority. The method also includes matching queues to available egresses by matching queues classified within tiers with higher priorities before matching queues classified within tiers with lower priorities.