Anna L Wong

US Patent:

20060230092, Oct 12, 2006

Filed:

May 12, 2006

Appl. No.:

11/433369

Inventors:

Alvin Ching - Sunnyvale CA, US
Jennifer Wong - Fremont CA, US
Bernard New - Carmel Valley CA, US
James Simkins - Park City UT, US
John Thendean - Berkeley CA, US
Anna Wong - Santa Clara CA, US
Vasisht Vadi - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/38

US Classification:

708490000

Abstract:

A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.

US Patent:

20060230096, Oct 12, 2006

Filed:

May 12, 2006

Appl. No.:

11/433517

Inventors:

John Thendean - , US
Jennifer Wong - Fremont CA, US
Bernard New - Carmel Valley CA, US
Alvin Ching - Sunnyvale CA, US
James Simkins - Park City UT, US
Anna Wong - Santa Clara CA, US
Vasisht Vadi - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/50

US Classification:

708700000

Abstract:

An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.