Andre Wong

US Patent:

8193634, Jun 5, 2012

Filed:

Sep 10, 2010

Appl. No.:

12/880025

Inventors:

Andre Wong - Santa Clara CA, US
Sukbhir Bajwa - Milpitas CA, US

International Classification:

H01L 21/00

US Classification:

257717, 257735, 257E23006, 257E23101, 257E23111, 257E29022

Abstract:

A method for mounting a semiconductor device onto a composite substrate, including a submount and a heat sink, is described. According to one aspect of the invention, the materials for the submount and the heat sink are chosen so that the value of coefficient of thermal expansion of the semiconductor device is in between the values of coefficients of thermal expansion of the materials of the submount and the heat sink, the thickness of the submount being chosen so as to equalize thermal expansion of the semiconductor device to that of the surface of the submount the device is mounted on. According to another aspect of the invention, the semiconductor device, the submount, and the heat sink are soldered into a stack at a single step of heating, which facilitates reduction of residual post-soldering stresses.

US Patent:

20090008773, Jan 8, 2009

Filed:

Jul 2, 2008

Appl. No.:

12/167125

Inventors:

Andre Wong - Santa Clara CA, US
Sukbhir Bajwa - Milpitas CA, US

Assignee:

JDS Uniphase Corporation - Milpitas CA

International Classification:

H01L 23/36
H01L 21/02

US Classification:

257720, 438122, 257E21002, 257E2311

Abstract:

A method for mounting a semiconductor device onto a composite substrate, including a submount and a heat sink, is described. According to one aspect of the invention, the materials for the submount and the heat sink are chosen so that the value of coefficient of thermal expansion of the semiconductor device is in between the values of coefficients of thermal expansion of the materials of the submount and the heat sink, the thickness of the submount being chosen so as to equalize thermal expansion of the semiconductor device to that of the surface of the submount the device is mounted on. According to another aspect of the invention, the semiconductor device, the submount, and the heat sink are soldered into a stack at a single step of heating, which facilitates reduction of residual post-soldering stresses.