Andrew P Kelm

US Patent:

59180315, Jun 29, 1999

Filed:

Dec 18, 1996

Appl. No.:

8/769068

Inventors:

Michael J. Morrison - Santa Clara CA
Andrew Paul Kelm - Fremont CA
Nazar A. Zaidi - San Jose CA
Bharat N. Zaveri - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 930

US Classification:

395384

Abstract:

A microarchitecture that accommodates divergent instruction sets having different data sizes and addressing modes utilizes a mechanism for translating a generic flow for an instruction into specific operations at run-time. These generic flows use a special class of micro-ops (uops), called "super-uops" (or "Suops)" which are translated into a variable number of regular (i. e. , simple) uops. A first-level decoder translates macroinstructions into either simple micro-ops or one or more super-uops which represent one or more sequences of one or more simple uops. A second-level decoder is responsible for converting the super-uops into the appropriate micro-op sequence based upon a set of arguments associated with the super-uop and attributes of the macroinstruction.