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Adnan Khaleel

age ~53

from Austin, TX

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Also known as:
  • Adnan Khaleel Lee
  • Khaleel I Adnan
Phone and address:
10430 Morado Cir, Austin, TX 78759
Related to:
Connected to:

Adnan Khaleel Phones & Addresses

  • 10430 Morado Cir, Austin, TX 78759
  • 1706 Summit View Pl APT 5, Austin, TX 78703 • 512 689-8514
  • 2801 Wells Branch Pkwy, Austin, TX 78728
  • 4110 College Main St, Bryan, TX 77801
  • College Station, TX
  • 10430 Morado Cir APT 2111, Austin, TX 78759

Work

  • Position:
    Homemaker

Resumes

Adnan Khaleel Photo 1

Adnan Khaleel

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Location:
Austin, Texas Area
Industry:
Computer Hardware
Skills:
High Performance Compuing
Multiprocessor System
Mergers and Acquisitions
Business Analysis
Business Strategy
New Business Development
International Business
Financial Modeling
Financial Analysis
Corporate Finance
Computer Architecture
Business Valuation
Business Intelligence
Big Data
Competitive Analysis
Technical Marketing
Strategic Planning
Due Diligence
Competitive Intelligence
Entrepreneurship
Cloud Computing
Valuation
Mergers
High Performance Computing
Strategy Development
Business Planning
Market Analysis
Product Management
Product Strategy
Start-ups
Business Management
Business Modeling
Marketing Strategy
Go-to-market Strategy
Multiprocessing
Strategy
Management
Integration
Product Development
Languages:
French
Adnan Khaleel Photo 2

Senior Director, Global Sales Strategist - Hpc And Artificial Intelligence

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Location:
10430 Morado Cir, Austin, TX 78759
Industry:
Information Technology And Services
Work:
Dell
Senior Director, Global Sales Strategist - Hpc and Artificial Intelligence
Cray Inc. Jun 2013 - Oct 2015
Director Product Management and Marketing Manager, Urika-Xa Big Data Platform For Hadoop and Spark
Yarcdata Oct 2012 - Jun 2013
Senior Manager Business Development, Partnerships and Alliances
Yarcdata Nov 2011 - Oct 2012
Senior Product and Marketing Manager, Urika-Gd Big Data Graph Analytics Appliance
Cray Inc. Aug 2007 - Nov 2011
Senior Manager Business Strategy
Education:
The University of Texas at Austin 2006 - May 2009
Master of Business Administration, Masters, Marketing, Entrepreneurship Texas A&M University Aug 1999
Master of Science, Masters Texas A&M University 1997 - 1999
Masters, Electrical Engineering Drexel University
Master of Science, Masters, Electrical Engineering
Skills:
Strategy
Competitive Analysis
Product Management
Start Ups
Go To Market Strategy
Management
Cloud Computing
Big Data
Integration
Business Strategy
Marketing Strategy
Product Development
Business Analysis
Analytics
High Performance Computing
Hardware
Solution Selling
Business Intelligence
Strategic Planning
Computer Architecture
Asic
Analysis
Processors
Hardware Architecture
Microprocessors
Entrepreneurship
New Business Development
Financial Modeling
Due Diligence
Competitive Intelligence
Semiconductors
Debugging
Market Analysis
Financial Analysis
Corporate Finance
Mergers
Business Planning
Multiprocessing
Eda
Embedded Systems
High Performance Compuing
Mergers and Acquisitions
Business Valuation
Technical Marketing
Strategy Development
Product Strategy
Business Modeling
Hadoop
Appliances
Pragmatic Marketing Certification
Languages:
French
Certifications:
Solutions Selling, Pragmatic Product Management

Us Patents

  • Histogram Performance Counters For Use In Transaction Latency Analysis

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  • US Patent:
    20050177344, Aug 11, 2005
  • Filed:
    Feb 9, 2004
  • Appl. No.:
    10/775974
  • Inventors:
    Adnan Khaleel - Austin TX, US
  • International Classification:
    G06F011/30
  • US Classification:
    702186000
  • Abstract:
    Methods and apparatus are described for measuring latency in computer systems. A computer system includes a processor, memory, and I/O. The processor is operable to initiate transactions involving the memory and the I/O. The computer system further includes a latency counter operable to measure a latency for each of selected ones of the transactions. The system also includes a plurality of histogram counters. Each histogram counter is operable to count the latencies corresponding to an associated latency range.

  • Reducing Probe Traffic In Multiprocessor Systems

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  • US Patent:
    20070055826, Mar 8, 2007
  • Filed:
    Oct 15, 2004
  • Appl. No.:
    10/966161
  • Inventors:
    Eric Morton - Austin TX, US
    Rajesh Kota - Austin TX, US
    Adnan Khaleel - Austin TX, US
    David Glasco - Austin TX, US
  • International Classification:
    G06F 13/28
  • US Classification:
    711141000
  • Abstract:
    A computer system having a plurality of processing nodes interconnected by a first point-to-point architecture is described. Each processing node has a cache memory associated therewith. A probe filtering unit is operable to receive probes corresponding to memory lines from the processing nodes and to transmit the probes only to selected ones of the processing nodes with reference to probe filtering information. The probe filtering information is representative of states associated with selected ones of the cache memories.
Name / Title
Company / Classification
Phones & Addresses
Adnan Khaleel
Director
SYMBIOSOCIAL INCORPORATED
PO Box 6009, Austin, TX 78762

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Adnan Khaleel

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