William T Mann

Author:

William P. Mann

ISBN #:

0672304503

Author:

William E. Mann

ISBN #:

0742542319

Author:

William E. Mann

ISBN #:

0742542327

Author:

William J. Mann

ISBN #:

0140275681

Author:

William J. Mann

ISBN #:

0525943358

Author:

William J. Mann

ISBN #:

0443089582

Author:

William J. Mann

ISBN #:

0452278562

Author:

William J. Mann

ISBN #:

0670030171

US Patent:

20130246433, Sep 19, 2013

Filed:

Mar 15, 2012

Appl. No.:

13/421761

Inventors:

Matthew Steven Fuller - Medfield MA, US
Mingsheng Hong - North Billerica MA, US
Hongmin Fan - Arlington MA, US
Andrew Allinson Lamb - Boston MA, US
William F. Mann - Sudbury MA, US
Lakshmikant Shrinivas - Billerica MA, US

International Classification:

G06F 17/30

US Classification:

707740, 707758, 707E17039

Abstract:

A record-pattern expression of a record pattern of data records is translated to a character-pattern expression of a character pattern. A data-record series of data records is converted to a character string in which each character in the character string corresponds to a respective data record in the data-record series. Pattern instances of the character pattern in the character string are searched to identify ordinal character positions in the character string of characters in the character pattern instances. Data records at ordinal record positions in the record series of data records corresponding to the ordinal character positions are reported.

US Patent:

57614130, Jun 2, 1998

Filed:

Jun 5, 1995

Appl. No.:

8/462759

Inventors:

Steven J. Frank - Hopkinton MA
William F. Mann - Sudbury MA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1100

US Classification:

39518502

Abstract:

A multiprocessor system has a plurality of processing cells, each including a processor and memory, interconnected via a network. The memories respond to requests by the processors for accessing data and, absent fault, transmitting it in response packets to at least to the requesting processors. A fault containment element responds to at least certain faults during access or transmission of a datum for including within the respective response packet a fault signal that prevents the requestor from accessing the datum. If a fault is detected in a datum not previously detected as faulty, a marking element can include a "marked fault" signal in the response packet. Whereas, it can include an "unmarked fault" signal when it detects a fault associated with a requested datum, but not specifically isolated to that datum. When a request is made for a datum which had previously been detected as faulty, the marking element can include in the response packet a "descriptor fault" signal. This facilitates identification of a particular source of an error and prevents that error from propagating to other processing cells.

US Patent:

53353250, Aug 2, 1994

Filed:

Mar 26, 1990

Appl. No.:

7/499182

Inventors:

Steven J. Frank - Hopkinton MA
Henry Burkhardt - Manchester MA
James B. Rothnie - Brookline MA
William F. Mann - Sudbury MA

Assignee:

Kendall Square Research Corporation - Waltham MA

International Classification:

G06F 1314

US Classification:

395200

Abstract:

An improved digital packet switching apparatus enabling enhanced packet transmission and high bandwidth packet transfer. The digital packet switching methods and apparatus permit selectively switching digital signal packet between a set of nodes. The invention includes multiple processing cells, each having a processor coupled to an associated content-addressable memory element. Packet processors, electrically coupled to the memory elements, selectively receive packets from the nodes and transmit the packets into at least one of the plural memory elements; or receive packets from the memory elements and transmit the packets to at least one of the nodes.

US Patent:

55353932, Jul 9, 1996

Filed:

Jun 5, 1995

Appl. No.:

8/461178

Inventors:

Christopher L. Reeve - Brookline MA
Tani Shavit - Lexington MA
James B. Rothnie - Brookline MA
Timothy G. Peters - Waltham MA
Linda Q. Lee - Cambridge MA
William F. Mann - Sudbury MA
Jacklin Kotikian - Concord MA

International Classification:

G06F 906

US Classification:

395700

Abstract:

An improved parallel processing apparatus and method executes an iterative sequence of instructions by arranging the sequence into subtasks and allocating those subtasks to processors. This division and allocation is conducted in such a manner as to minimize data contention among the processors and to maximize the locality of data to them. The improved apparatus and method have application to a variety of multiprocessor systems, including those which are massively parallel.

US Patent:

52513084, Oct 5, 1993

Filed:

Jun 22, 1989

Appl. No.:

7/370287

Inventors:

Steven J. Frank - Hopkinton MA
Henry Burkhardt - Manchester MA
James B. Rothnie - Brookline MA
Benson I. Margulies - Arlington MA
Frederick D. Weber - Concord MA
Linda Q. Lee - Cambridge MA
Glen Dudek - Woburn MA
William F. Mann - Sudbury MA
Edward N. Kittlitz - Cambridge MA
Ruth Shelley - Upton MA

Assignee:

Kendall Square Research Corporation - Waltham MA

International Classification:

G06F 1300

US Classification:

395425

Abstract:

A digital data processing system includes a plurality of central processor units which share and access a common memory through a memory management element. The memory management element permits, inter alia, data in the common memory to be accessed in at least two modes. In the first mode, all central processing units requesting access to a given datum residing in memory are signalled of the datum's existence. In the second mode, only selected central processing units requesting access to a resident datum are notified that it exists, while others requesting access to the datum are signalled that it does not exist. The common memory can include a plurality of independent memory elements, each coupled to and associated with, a respective one of the central processing units. A central processing unit can include a post-store element for effecting the transfer of copies of data stored in its associated memory element to a memory element associated with another central processing unit.

US Patent:

20160161696, Jun 9, 2016

Filed:

Feb 12, 2016

Appl. No.:

15/042729

Inventors:

- Hickory NC, US
William H. Mann - Boston MA, US

International Classification:

G02B 6/44
B05D 3/10
B05D 7/00
G02B 6/48
G02B 6/46

Abstract:

A system and method for installing a fiber or cable on a wall or ceiling of a structure includes providing a fiber, wire or cable pre-coated with a hot melt adhesive that simply needs to be activated by the application of sufficient heat for a sufficient amount of time immediately before installation. Rolls or cartridges of wire or cable pre-coated with the hot melt adhesive are provided. The hot melt adhesive coated wire or cable is fed through a heated chamber, preferably a tip on a portable heating device such as a battery operated soldering iron, which activates the pre-coated hot melt adhesive prior to utilizing the heating tip to apply pressure to the adhesive wire directly to a wall or ceiling thereby adhering the fiber, wire or cable to the desired surface.