Tom A Agan

US Patent:

7206221, Apr 17, 2007

Filed:

Sep 9, 2005

Appl. No.:

11/223159

Inventors:

Tom Allen Agan - Saint Paul MN, US
James Chyi Lai - Saint Paul MN, US
Chien-Chiang Chan - Chung-Ho, TW

Assignee:

Northern Lights Semiconductor Corp. - St. Paul MN

International Classification:

G11C 11/00

US Classification:

365158, 365104, 36518908

Abstract:

An upside-down MRAM comprises a sense transistor and a plurality of sense lines. A first end of the sense transistor is electrically connected to a low voltage. The sense lines are electrically connected in parallel between a high voltage and a second end of the sense transistor. Each of the sense lines has a control logic and at least one memory bit, and the memory bit is connected in series between the high voltage and the control logic.

US Patent:

7397285, Jul 8, 2008

Filed:

Oct 16, 2006

Appl. No.:

11/549719

Inventors:

Tom Allen Agan - Saint Paul MN, US
James Chyi Lai - Saint Paul MN, US

Assignee:

Northern Lights Semiconductor Corp. - Saint Paul MN

International Classification:

H03K 19/20

US Classification:

326104, 365158

Abstract:

A magnetic transistor circuit with the AND, NAND, NOR and OR functions has a first, a second, a third, a fourth magnetic transistor, and a routing line. These four magnetic transistors act as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The AND, NAND, NOR and OR logic functions of the binary system can be implemented by the control of these metal devices.

US Patent:

7405599, Jul 29, 2008

Filed:

Oct 16, 2006

Appl. No.:

11/549722

Inventors:

Tom Allen Agan - Saint Paul MN, US
James Chyi Lai - Saint Paul MN, US

Assignee:

Northern Lights Semiconductor Corp. - Saint Paul MN

International Classification:

H03K 19/20

US Classification:

326104, 326 37, 326136

Abstract:

A magnetic transistor circuit with the OR, NOR, NAND and AND functions has a first, a second, a third, a fourth magnetic transistor, and a routing line. These four magnetic transistors as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The OR, NOR, NAND and AND logic functions of the binary system can be implemented by the control of these metal devices.

US Patent:

7492021, Feb 17, 2009

Filed:

Oct 16, 2006

Appl. No.:

11/549726

Inventors:

James Chyi Lai - Saint Paul MN, US
Tom Allen Agan - Saint Paul MN, US

Assignee:

Northern Lights Semiconductor Corp. - Saint Paul MN

International Classification:

H01L 29/82

US Classification:

257422, 257E29167

Abstract:

A magnetic transistor includes a magnetic section, a thin semiconductor layer, a first metal terminal, a second metal terminal, and a third metal terminal. The thin semiconductor layer is disposed on the magnetic section. The first metal terminal is disposed on one end of the magnetic section, acting as a gate of the magnetic transistor and capable of providing a conductive channel in the thin semiconductor layer. The second metal terminal and the third metal terminal are disposed respectively on one end and the other end of the thin semiconductor layer, capable of creating a conductive region. While the magnetic transistor is turned on, a current path is formed between the second metal terminal and the third metal terminal via the thin semiconductor layer.

US Patent:

7539046, May 26, 2009

Filed:

Jan 31, 2007

Appl. No.:

11/669409

Inventors:

James Chyi Lai - Saint Paul MN, US
Tom Allen Agan - Saint Paul MN, US

Assignee:

Northern Lights Semiconductor Corp. - Saint Paul MN

International Classification:

G11C 11/14

US Classification:

365158, 365171, 365173, 365131, 365 66

Abstract:

An integrated circuit with magnetic memory has a silicon transistor layer, at least one magnetic memory layer, and a metal routing layer. The silicon transistor layer is arranged to generate several logic operation functions. The magnetic memory layer is arranged to store the data required by the logic operation functions. The metal routing layer has several conducting lines to transmit the data between the silicon transistor layer and the magnetic memory layer.

US Patent:

7847586, Dec 7, 2010

Filed:

Aug 20, 2007

Appl. No.:

11/841193

Inventors:

Tom Allen Agan - Saint Paul MN, US
James Chyi Lai - Saint Paul MN, US

Assignee:

Northern Lights Semiconductor Corp. - St. Paul MN

International Classification:

H03K 19/173
H01L 25/00

US Classification:

326 38, 326 37, 326 47

Abstract:

A logic gate array is provided. The logic gate comprises a silicon substrate, a first logic gate layer on top of the silicon substrate, a second logic gate layer on top of the first logic gate layer, and a routing layer between the first and second logic gate layers for routing magnetic gates in the first and second logic gate layers, wherein the first logic gate layer, the second logic gate layer, and the routing layer are electrically connected by vias.

US Patent:

8405421, Mar 26, 2013

Filed:

May 30, 2012

Appl. No.:

13/483452

Inventors:

Alexander Mikhailovich Shukh - Savage MN, US
Tom A. Agan - Maple Grove MN, US

International Classification:

G06F 7/50

US Classification:

326 55, 326121, 708670

Abstract:

A nonvolatile full adder circuit comprising a full adder electrical circuitry comprising three input terminals for receiving two input and carry-in signals, a sum output terminal, and an carry-out output terminal; first and second nonvolatile memory elements electrically coupled to the first and second output terminal, respectively at their first ends and to an intermediate voltage source at their second ends. The nonvolatile memory elements comprise two stable logic states. A logic state each of the of the nonvolatile memory elements is controlled by a bidirectional electrical current running between its first and second ends. The full adder circuitry is electrically coupled to a high voltage source at its first source terminal and to a low voltage source at its second source terminal, wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source.

US Patent:

20060268602, Nov 30, 2006

Filed:

May 19, 2006

Appl. No.:

11/437474

Inventors:

Tom Agan - Plymouth MN, US
James Lai - Plymouth MN, US
Chien-Chiang Chan - Chung-Ho City, TW

International Classification:

G11C 11/00

US Classification:

365158000

Abstract:

A memory comprises a plurality of memory units electrically connected. Each of the memory units comprises a pull-down transistor, a plurality of column lines and a selector. Each of the column lines has at least one bit. The selector is electrically connected between the pull-down transistor and the column lines. The selector is arranged to select one from the column lines to be accessed by the pull-down transistor. This results in a memory design that is faster, has more capability, is cheaper to build, quieter, and lower power.