Sunil A Patel

US Patent:

6335491, Jan 1, 2002

Filed:

Feb 8, 2000

Appl. No.:

09/499801

Inventors:

Maniam Alagaratnam - Cupertino CA
Kishor V. Desai - Fremont CA
Sunil A. Patel - Los Altos CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H05K 116

US Classification:

174260, 174261, 174262, 361760, 257686, 257738, 257778

Abstract:

The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate. Advantageously, the improved thermal performance of the present invention may allow larger substrates, larger dies, larger solder ball arrays, reduced solder ball pitches and pin counts well above conventional levels without compromising semiconductor device reliability.

US Patent:

6433565, Aug 13, 2002

Filed:

May 1, 2001

Appl. No.:

09/846435

Inventors:

Kishor V. Desai - Fremont CA
Maniam Alagaratnam - Cupertino CA
Sunil A. Patel - Los Altos CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 3102

US Classification:

324755, 324765

Abstract:

A test fixture for a ball grid array package is disclosed that includes a test ball grid array package having a plurality of coarse pitch contacts formed on a coarse pitch surface of the test ball grid array package and a plurality of wafer bumps formed on a fine pitch surface of the test ball grid array package and an interposer coupled to the plurality of wafer bumps formed on the fine pitch surface of the test ball grid array package for coupling to a plurality of wafer bumps formed on a fine pitch surface of a subject ball grid array package.

US Patent:

6466038, Oct 15, 2002

Filed:

Nov 30, 2000

Appl. No.:

09/727427

Inventors:

Senol Pekin - San Jose CA
Sunil A. Patel - Los Altos CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 3126

US Classification:

324719, 324537, 324717, 3241581

Abstract:

A method for measuring electromigration includes the steps of measuring a corresponding voltage increase across an interconnect as a function of time for a plurality of nonzero heating rates and calculating an interconnect integrity from the voltage increase.

US Patent:

6618938, Sep 16, 2003

Filed:

Oct 9, 2001

Appl. No.:

09/974157

Inventors:

Maniam Alagaratnam - Cupertino CA
Kishor V. Desai - Fremont CA
Sunil A. Patel - Los Altos CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H05K 334

US Classification:

29840, 29739, 29825, 29832, 22818021, 22818022

Abstract:

The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate. Advantageously, the improved thermal performance of the present invention may allow larger substrates, larger dies, larger solder ball arrays, reduced solder ball pitches and pin counts well above conventional levels without compromising semiconductor device reliability.

US Patent:

7383049, Jun 3, 2008

Filed:

Mar 7, 2002

Appl. No.:

10/093751

Inventors:

Alkinoos H. Vayanos - San Diego CA, US
Bruce Wilson - Palo Alto CA, US
Richard John Girerd - Mountain View CA, US
Grant Marshall - Campbell CA, US
Mark Moeglein - Ashland OR, US
Roland Rick - San Diego CA, US
Scott Smith - San Jose CA, US
Sunil Patel - San Jose CA, US
Wyatt Riley - Fremont CA, US
Zoltan Biacs - San Mateo CA, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H04Q 7/20

US Classification:

4554561, 4554042, 4554142, 4554221, 455423, 34235702

Abstract:

In a wireless telecommunication network, hybrid (GPS and AFLT) mobile stations provide redundant position information, which is used for time base calibration and/or correction of position measurements. Every mobile station (i. e. , handset or cellular phone) can be used as a test instrument, and data from regular wireless phone calls can be supplemented by data from drive-around field test units. The time base and/or position offsets are stored in a base station almanac data base along with other information used for obtaining the most reliable position fixes under a variety of conditions. An automatic system is provided for creating, updating, and maintaining the base station almanac data base. The automatic system not only characterizes the performance of the wireless network but also characterizes the performance of the position determination system. The automatic system provides performance feedback to system operators and customers.

US Patent:

20100093377, Apr 15, 2010

Filed:

Jun 11, 2009

Appl. No.:

12/483145

Inventors:

Wyatt Thomas Riley - King of Prussia PA, US
Mark L. Moeglein - Ashland OR, US
James D. Deloach - Los Altos CA, US
Alkinoos Hector Vayanos - Ann Arbor MI, US
Bruce E. Wilson - Palo Alto CA, US
Grant Alexander Marshall - Santa Clara CA, US
Roland Reinhard Rick - Superior CO, US
Sunil Patel - San Jose CA, US
Zoltan F. Biacs - Sam Mateo CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H04W 24/00

US Classification:

4554566

Abstract:

In a wireless mobile communication system having a position determination service, base station information is stored in a base station almanac. In addition to the position of the base station antenna, forward link delay calibration, and base station identification information, a base station almanac record includes the center location of the base station sector coverage area, the maximum range of the base station antenna, the terrain average height over the sector coverage area, the terrain height standard deviation over the sector coverage area, round-trip delay (RTD) calibration information, repeater information, pseudo-random noise (PN) increments, uncertainty in the base station antenna position, uncertainty in the forward-link delay calibration, and uncertainty in the round-trip delay calibration.

US Patent:

59090570, Jun 1, 1999

Filed:

Sep 23, 1997

Appl. No.:

8/935424

Inventors:

John P. McCormick - Palo Alto CA
Sunil A. Patel - Los Altos CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2302
H01L 2334
H05K 720

US Classification:

257704

Abstract:

Provided is a single-piece integrated heat spreader/stiffener which is bonded to the substrate and die in a semiconductor package following electrical bonding of the die to the substrate, a packaging method using the integrated heat spreader/stiffener, and a semiconductor package incorporating the integrated heat spreader/stiffener. In a preferred embodiment, the integrated heat spreader/stiffener is a piece of high modulus, high thermal conductivity material shaped to attach over a die on the surface of a packaging substrate. The heat spreader/stiffener is equipped with a plurality of apertures to provide access to the top surface of the die for adhesive to bond the heat spreader/stiffener to the die, and to its perimeter to provide access for dispensation of underfill material between the die and the substrate. Once the adhesive and underfill materials are in place, the adhesive and underfill resins are cured by heating. A ball grid array (BGA) process may then be used to apply solder balls to the underside of the substrate for subsequent bonding of the package to a circuit board for use.

US Patent:

60021713, Dec 14, 1999

Filed:

Sep 22, 1997

Appl. No.:

8/935834

Inventors:

Kishor V. Desai - Livermore CA
Sunil A. Patel - Los Altos CA
John P. McCormick - Palo Alto CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2310
H01L 2334

US Classification:

257707

Abstract:

Provided is a multi-piece integrated heat spreader/stiffener assembly which is bonded to the substrate and die in a semiconductor package following electrical bonding of the die to the substrate, a packaging method using the integrated heat spreader/stiffener, and a semiconductor package incorporating the integrated heat spreader/stiffener. In a preferred embodiment, the integrated heat spreader/stiffener assembly has two pieces, both composed of a high modulus, high thermal conductivity material shaped to attach to each other and a die on the surface of a packaging substrate. A first piece of this assembly is bonded to the substrate surface adjacent to an electrically connected die and to the top surface of the die prior to the dispensation and curing of underfill material which provides the mechanical connection between the die and the substrate. With the first piece of the assembly in place, access may still be had to at least one edge of the die to dispense and cure the underfill epoxy. Once the underfill material is cured by heating, the second piece of the assembly is placed and bonded on the substrate either abutting or overlapping with the first piece.