Mohammad Shamsur Rahman

Author:

Mohammad A. Rahman

ISBN #:

0890063060

US Patent:

6687779, Feb 3, 2004

Filed:

Jul 14, 2000

Appl. No.:

09/616105

Inventors:

Gordon L. Sturm - Dallas TX
Nilay Mitash - Murphy TX
Mohammad Jahidur Rahman - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1314

US Classification:

710305

Abstract:

A bus interface device includes a parallel input configured to be coupled to a bus ( ), such as a primary PCI bus. The device also includes a parallel data output (TXD) and at least two control output nodes (TX_ER and TX_EN). Data control circuitry coupled to the control output nodes utilizes a coding scheme (e. g. , an 8B/10B scheme) to generate one of a set of control codes (e. g. , Idle, Extend, Normal Data and Error) to be provided to the control output nodes. The device also includes reset control circuitry that generates a specified sequence of control codes (e. g. , a sequence of Idles and Extends) on the control outputs. This sequence can be used to communicate information such as a signal (e. g. , reset signal) and/or a mode (e. g. , a CRC mode).

US Patent:

6928569, Aug 9, 2005

Filed:

Jul 19, 2002

Appl. No.:

10/199261

Inventors:

Mohammad Jahidur Rahman - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04L007/00

US Classification:

713400, 713401

Abstract:

A method for application in a data interface controller receiving asynchronous input data at predetermined one of a plurality of input bit frequencies, wherein the input data is sampled by the interface controller at a sample rate greater than the predetermined input bit rate, and wherein the sample rate is variable, and wherein the interface controller provides output data corresponding to the input data, but delayed by a delay amount that varies in accordance with the sample rate. The method is for providing a responsive signal event, responsive to a reference event in the delayed input data and at a predetermined time relative to an input bit time. In the method, a reference timing number is stored, representing the predetermined time in periods of the predetermined input bit frequency. An adjustment number corresponding to the delay amount is determined, in periods of the predetermined input bit frequency. The adjustment number is subtracted from the reference timing value to determine an adjusted timing number.

US Patent:

6981204, Dec 27, 2005

Filed:

Jul 19, 2002

Appl. No.:

10/199723

Inventors:

Takeshi Sakai - Richardson TX, US
Rameshkumar Ravikumar - Plano TX, US
Mohammad Jahidur Rahman - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F011/08
H03M013/00

US Classification:

714797, 714700, 714709

Abstract:

An apparatus and a method for filtering glitches in a data communications controller receiving asynchronous input data signals varying between two signal levels representing two bit values and having a predetermined input bit period, and sending output data signals corresponding to the input data signals. Glitches are detected in the input data signals by detecting reversals of signal level having a duration less than the input bit period. A glitch time value corresponding to the glitch duration is determined, and then a sampling clock rate is set at a rate determined from the glitch time value. The input data signals are sampled at the sampling clock rate to generate a sequence of input data samples. A voting number of input data samples are monitored and an output signal is provided, representing the value of a majority of the sequential input data samples.

US Patent:

7501981, Mar 10, 2009

Filed:

Jun 8, 2006

Appl. No.:

11/449239

Inventors:

Mohammad Atiqur Rahman - Allen TX, US
Alan Martin Gilkes - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01S 1/00
H04B 7/185

US Classification:

34235702, 34235703, 34235706

Abstract:

Methods and apparatus to detect integrity failures in satellite position system (SPS) receivers are disclosed. An example method comprises estimating a position fix from a plurality of pseudoranges, computing a zero-mean error vector based upon the position fix; and determining if an integrity failure has occurred based on the zero-mean error vector.

US Patent:

7541884, Jun 2, 2009

Filed:

Oct 31, 2007

Appl. No.:

11/932258

Inventors:

Mohammad A. Rahman - Allen TX, US
Umashankar S. Iyer - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03L 1/02
H04B 1/06
H04L 7/00
H04L 27/06

US Classification:

331176, 375344, 375354, 455257

Abstract:

In at least some disclosed embodiments, a method includes receiving a burst of data out of multiple bursts of data subject to long-term frequency drift and short-term frequency drift, determining an intercept of the long-term frequency drift based on, at most, the entire burst, and compensating for the long-term drift of a subsequent burst based on the intercept. The method further includes determining a slope of the short-term frequency drift, and compensating for the short-term frequency drift of a subsequent burst based on the slope.

US Patent:

7650528, Jan 19, 2010

Filed:

Jun 7, 2007

Appl. No.:

11/759313

Inventors:

Mohammad Jahidur Rahman - Richardson TX, US
Sabuson George - Parker TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 11/00

US Classification:

714 3

Abstract:

A system and method for making efficient use of fuse ROM redundancy to increase yield and security. Some embodiments provide a memory repair system including a non-volatile memory component and a controller coupled to the non-volatile memory component. The non-volatile memory component includes a plurality of memory locations. The plurality of memory locations includes a replacement memory location to replace a faulty memory location and a replacement indicia memory location to store replacement memory location indicia. The controller coupled to the non-volatile memory component reads replacement memory location indicia from the replacement indicia memory location, determines an address for the replacement memory location using the indicia, reads the replacement memory location, and transfers a data value contained in the replacement memory location to a second memory component to repair a defective memory location of the second memory component.

US Patent:

7656695, Feb 2, 2010

Filed:

Sep 10, 2007

Appl. No.:

11/852687

Inventors:

Mohammad Jahidur Rahman - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 17/00

US Classification:

365 96, 3652257

Abstract:

An electronic fuse system and method are disclosed employing a fuse ROM having one or more blocks of memory. Each block of memory comprises a plurality of words with at least one word of the plurality of words containing security bits associated with a respective block. An electronic fuse controller is in communication with the fuse ROM and one or more external devices that are configured to request one or more words that reside in the fuse ROM from the electronic fuse controller. At least one security register includes indication bits that provide an indication whether security bits have been obtained for a respective block of memory of the fuse ROM after a power down and power up cycle. The electronic fuse controller provides the requested word if an indication bit associated with the block of memory is set.

US Patent:

7895489, Feb 22, 2011

Filed:

Oct 10, 2008

Appl. No.:

12/249317

Inventors:

Mohammad Jahidur Rahman - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 31/28

US Classification:

714729

Abstract:

An aspect of the present invention is drawn to a system that includes an automatic test engine, a decompressor, a first scan chain, a second scan chain, a compactor and a debug output. The automatic test engine is operable to output a test output, to receive a resultant input, to receive a debug input, to monitor the debug input and to compare the test output with the resultant input. The decompressor is arranged to receive a decompressor input based on the test output, to output a decompressor output. The scan chains are arranged to receive input based on the decompressor output, and each scan chain includes at least one flip-flop. The compactor is arranged to receive input based output from the flip-flops, and to output a compactor output. The debug output line is arranged to receive the flip-flop output.

Address:

6152 Edsall Rd APT 203, Alexandria, VA 22304

VIN:

JHLRE48747C049182

Make:

HONDA

Model:

CR-V

Year:

2007

Address:

6101 Declaration Sq, Alexandria, VA 22312

VIN:

JTDBR32E370101861

Make:

TOYOTA

Model:

COROLLA

Year:

2007