Kyung M Lee

US Patent:

6501302, Dec 31, 2002

Filed:

Oct 15, 2001

Appl. No.:

09/977770

Inventors:

Kyung T. Lee - Santa Clara CA
Jason M. Hart - Santa Clara CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G01R 1500

US Classification:

327 55, 327 57

Abstract:

A single-input/dual output sense amplifier includes cross-coupled transistors connected to a reference voltage; a first input transistor and a second input transistor connected to the cross-coupled transistors, wherein the first input transistor is coupled to a single input bit-line and the second input transistor is coupled to a reference voltage; an inverter receiving the input bit-line signal and outputting a complement of the input bit-line signal; a control circuit coupled to the second input transistor and receiving the complement of the input bit-line signal, wherein the cross-coupled transistors produce dual differential outputs. A method of producing dual differential output signals from a single input signal includes receiving a single input bit-line signal; inverting the received single input bit-line signal to produce the complement of the received single input bit-line signal; controlling the charging and discharging of a reference node based on the complement of the received input bit-line signal; and outputting dual differential output signals based on the single input bit-line signal and the reference node.

US Patent:

6594679, Jul 15, 2003

Filed:

Mar 20, 2000

Appl. No.:

09/531850

Inventors:

Kyung Tek Lee - Sunnyvale CA
Kevin John Nowka - Round Rock TX
Sang Hoo Dhong - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1500

US Classification:

708211

Abstract:

A leading-zero anticipator having an independent sign bit determination module is disclosed. An apparatus for anticipating leading zeros for an adder within a floating-point processor includes a leading-zero anticipator and a sign determination module. The leading-zero anticipator generates a leading zeros string and a leading ones string by examining carry propagates, generates, and kills of two adjacent bits of two input operands of the adder. The leading zeros string is intended for a positive sum, and the leading ones string is intended for a negative sum. Independent of the leading-zero anticipator, the sign determination module determines a sign of the output of the adder in concurrence with the operations within the leading-zero anticipator.

US Patent:

6766264, Jul 20, 2004

Filed:

Aug 2, 2002

Appl. No.:

10/211681

Inventors:

Dae Suk Jung - Santa Clara CA
Kyung Lee - Santa Clara CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1100

US Classification:

702107, 702191, 716 4

Abstract:

One embodiment of the present invention provides a system for calibrating a model of a digital circuit to account for noise effects between signal lines. The system operates by first fabricating a digital circuit for calibration purposes. Next, an input signal is applied to an aggressor net within the digital circuit. The system then measures how noise from the input signal affects the amplitude of a signal on a victim net within the digital circuit. Finally, the system adjusts parameters of the circuit model using the measured results.

US Patent:

7256619, Aug 14, 2007

Filed:

Apr 4, 2005

Appl. No.:

11/099186

Inventors:

Yonghee Im - Pleasanton CA, US
Kyung T. Lee - San Jose CA, US
Han Bin Kim - Pleasanton CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H03K 19/096
H03K 19/20

US Classification:

326 95, 326121, 365203, 327544

Abstract:

A method and apparatus for shifting a dynamic circuit, driven by a one-shot clock, to a pre-charge mode, during a power-off mode, is provided. Under certain conditions, a floating node may be present in a dynamic circuit. One approach to prevent floating nodes involves the generation of a new one-shot clock signal that is supplied to the last dynamic circuit in the series of dynamic circuits before the output flop (“the final dynamic circuit”). The new one-shot clock signal is driven to a logical low value when the power-off signal has a logical high value. Another approach to prevent floating nodes involves modifying the final dynamic circuit to include a structure that, when the power-off signal has a logical high value, drives the dynamic node to either a logical high value or a logical low value to prevent the dynamic node from becoming a floating node.

US Patent:

20080109479, May 8, 2008

Filed:

Apr 1, 2004

Appl. No.:

10/551661

Inventors:

Lewis Cheng - Mountain View CA, US
Joseph Fusion - Portland OR, US
Kyung Lee - Fort Lee NJ, US

Assignee:

Plantii USA, Inc., - San Jose CA

International Classification:

G06F 17/30

US Classification:

7071041, 707E17122

Abstract:

Provided herein is a system, method and computer program product for effectively arranging and rendering multimedia information using for example, Macromedia's Flash™ technology, the Extensible Markup Language (XML) language and the Mathematical Markup Language (MathML). The invention utilizes question data (), possible visual aids (), possible descriptive solutions (), and element alignment ().

US Patent:

61821519, Jan 30, 2001

Filed:

Jul 29, 1996

Appl. No.:

8/688272

Inventors:

Hsiuying Cheng - Fremont CA
Jung-hsin Hu - San Jose CA
Kyung B. Lee - San Jose CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900
G06F 946
G06F 15163

US Classification:

709310

Abstract:

The present invention is directed to a storage management system. More particularly if relates to a client/server library system for storing objects in the library system in batches by avoiding storing those objects in an intermediary storage, such as in a client storage space or in a cache, before storing them in the library system. The invention includes a library server, object server and library client, in which an application program interacts with the library client for storing objects, or binary large objects (blobs), in the object server under control of the library server. The present invention provides for an application program to read in objects into a memory space allocated and managed by the application program, or into an application program memory space allocated and managed by the library client. When the library client stores the objects residing in the allocated memory space, copies of the objects are transferred directly from the allocated memory space to the object server without having another copy of the object first being made in the library client, such as in the library client storage space or in a client cache. Accordingly, batch storage of objects is accomplished more efficiently than in conventional library system.

US Patent:

20230009452, Jan 12, 2023

Filed:

Dec 11, 2020

Appl. No.:

17/784614

Inventors:

- Stanford CA, US
- Wolfsburg, DE
Yongmin KIM - Stanford CA, US
Thomas JARAMILLO - Stanford CA, US
Drew C. HIGGINS - Stanford CA, US
Maha YUSUF - Stanford CA, US
Zhaoxuan WANG - Stanford CA, US
Kyung Min LEE - Stanford CA, US
Marat ORAZOV - Stanford CA, US
Dong Un LEE - Stanford CA, US
Tanja GRAF - Wolfsburg, DE
Thomas SCHLADT - Wolfsburg, DE
Gerold HUEBNER - Wolfsburg, DE
Hanna-Lena WITTERN - Wolfsburg, DE
Jonathan Edward MUELLER - Wolfsburg, DE

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Stanford CA
Volkswagen Aktiengesellschaft - Wolfsburg

International Classification:

H01M 4/92
C23C 16/455
H01M 4/86
H01M 4/88
H01M 8/1004

Abstract:

A catalyst structure includes: (1) a substrate; (2) a catalyst layer on the substrate; and (3) an adhesion layer disposed between the substrate and the catalyst layer. In some implementations, an average thickness of the adhesion layer is about 1 nm or less. In some implementations, a material of the catalyst layer at least partially extends into a region of the adhesion layer. In some implementations, the catalyst layer is characterized by a lattice strain imparted by the adhesion layer.

US Patent:

20180005650, Jan 4, 2018

Filed:

Sep 13, 2017

Appl. No.:

15/703108

Inventors:

- Fremont CA, US
Mingjun Yu - Sunnyvale CA, US
Min Zheng - Milpitas CA, US
Kyung Lee - Fremont CA, US
Tsung Yuan Chen - San Ramon CA, US

International Classification:

G11B 5/31
C23C 14/58
G11B 5/855
G11B 5/00

Abstract:

A method for fabricating a near-field transducer (NFT) for a heat assisted magnetic recording (HAMR) write apparatus is described. The HAMR write apparatus is coupled with a laser for providing energy and has a media-facing surface (MFS) configured to reside in proximity to a media during use. The method includes providing a stack on an underlayer. The stack includes an endpoint detection layer, an optical layer and an etchable layer. The optical layer is between the etchable and endpoint detection layers. The etchable layer is patterned to form a mask. A portion of the optical layer is removed. A remaining portion of the optical layer has a bevel at a bevel angle from the MFS location. The bevel angle is nonzero and acute. The NFT is provided such that the NFT has an NFT front surface adjoining the bevel and at the bevel angle from the MFS location.