Kai Zhang

US Patent:

6492731, Dec 10, 2002

Filed:

Jun 27, 2000

Appl. No.:

09/605380

Inventors:

Wilbur G. Catabay - Saratoga CA
Wei-Jen Hsia - Sunnyvale CA
Kai Zhang - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2348

US Classification:

257758, 257760, 257411

Abstract:

A composite layer of low k dielectric material for integrated circuit structures comprising a thick lower conformal barrier layer of low k dielectric material, a low k center layer of carbon-doped silicon oxide dielectric material having good gap filling capabilities, and a thick upper conformal barrier layer of low k dielectric material. The thick lower conformal barrier layer of low k dielectric material protects the lower surface of the main low k dielectric layer and also protects against misaligned vias entering the main low k dielectric material below the height of the metal line without raising the capacitance of the structure as would a lower barrier layer of non-low k dielectric material. The thick upper conformal barrier layer of low k dielectric material protects the upper surface of the main low k dielectric layer, as well as to provide thickness for vias to pass through without risk of via poisoning, and without raising the capacitance of the structure as would a thick upper barrier layer of non-low k dielectric material.

US Patent:

6503840, Jan 7, 2003

Filed:

May 2, 2001

Appl. No.:

09/848758

Inventors:

Wilbur G. Catabay - Saratoga CA
Wei-Jen Hsia - Sunnyvale CA
Yong-Bae Kim - Cupertino CA
Kiran Kumar - Sunnyvale CA
Kai Zhang - Saratoga CA
Richard Schinella - Saratoga CA
Philippe Schoenborn - San Mateo CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21302

US Classification:

438694, 438699, 438700, 438702, 438709, 438718, 438725

Abstract:

A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus.

US Patent:

6559033, May 6, 2003

Filed:

Jun 27, 2001

Appl. No.:

09/892250

Inventors:

John Rongxiang Hu - San Jose CA
Kai Zhang - Saratoga CA
Senthil K. Arthanari - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2176

US Classification:

438444, 438622, 438623, 438692, 438733, 438597

Abstract:

Protective caps are formed over horizontally closely spaced apart metal lines of an integrated circuit structure. Low k silicon oxide dielectric material is then deposited over and between the metal lines and over protective caps on the lines. After the formation of such low k material between the lines and over the caps, standard k dielectric material is deposited over the low k layer as a planarizing layer over low portions of the low k layer between the lines which may be lower than the top of the caps on the lines to prevent further etching or dishing of the low k layer of during planarizing. The structure is then planarized to bring the low k dielectric material down to the tops of the protective caps on the metal lines. A layer of standard k silicon material is then formed over the planarized low k layer and the caps to allow via formation without passing through the low k layer to avoid via poisoning.

US Patent:

6559048, May 6, 2003

Filed:

May 30, 2001

Appl. No.:

09/870851

Inventors:

Yong-Bae Kim - Cupertino CA
Philippe Schoenborn - San Mateo CA
Kai Zhang - Saratoga CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 214763

US Classification:

438637, 438638, 438639, 438640, 438666, 438668

Abstract:

Via poisoning of vias formed in low k carbon-containing silicon oxide dielectric material is suppressed by forming the via in a layer of such dielectric material with a smooth inwardly sloped sidewall. Such a sloped sidewall via can be etched in a low k dielectric layer by first forming a via resist mask over the upper surface of such a dielectric layer, then heat treating the mask sufficiently to deform the sidewall geometry of the resist mask to form a sloped sidewall on the opening or openings in the heat treated resist mask. The resulting erosion of such a resist mask, during a subsequent etch step to form the via in the low k dielectric material through such a sloped sidewall resist mask, imparts a tapered or sloped sidewall geometry to the via which is then formed in the underlying layer of low k dielectric material. In a preferred embodiment, when the via is cut through several layers of different types of dielectric material, the smoothness of the sloped sidewall of the resulting via is enhanced by adjusting the selectivity of the via etch to uniformly etch each of the layers of dielectric material at approximately the same rate.

US Patent:

6713386, Mar 30, 2004

Filed:

Dec 19, 2001

Appl. No.:

10/025304

Inventors:

Rongxiang Hu - San Jose CA
Yongbae Kim - Cupertino CA
Sang-Yun Lee - Stanford CA
Hiroaki Takikawa - Chagasaki, JP
Shumay Dou - Saratoga CA
Sarah Neuman - San Mateo CA
Philippe Schoenborn - San Mateo CA
Keith Chao - Saratoga CA
Dilip Vijay - Foster City CA
Kai Zhang - Saratoga CA
Masaichi Eda - Gresham OR

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 214763

US Classification:

438639, 438660, 438633

Abstract:

A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

US Patent:

6735372, May 11, 2004

Filed:

Jun 4, 2002

Appl. No.:

10/163153

Inventors:

Dennis Chi Zhou - Cupertino CA
Kai Zhang - San Jose CA

Assignee:

Arasor Corporation - Mountain View CA

International Classification:

G02B 600

US Classification:

385140, 385147

Abstract:

The present invention is directed towards a channel power monitor for monitoring channel power levels for each of N signal channels. The value of each channel power level is designated as p( ), where is a channel parameter that characterizes each channel. An embodiment of the invention includes a variable channel attenuator having M attenuation profiles where M N, and where a k-th attenuation profile is characterized as a function of the channel parameter by A ( ). This embodiment also includes a detector for measuring a k-th integrated attenuated power level, the value of which is represented by P. An analysis unit receives all of the values P of the integrated attenuated power levels and thereupon derives the values p( ) of the channel power levels by solving a set of linear equations.

US Patent:

6767832, Jul 27, 2004

Filed:

Apr 27, 2001

Appl. No.:

09/844352

Inventors:

Kiran Kumar - Sunnyvale CA
Zhihai Wang - Sunnyvale CA
Wilbur G. Catabay - Saratoga CA
Kai Zhang - Saratoga CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 21302

US Classification:

438689, 438700, 438706, 438710, 438712

Abstract:

A method of processing a substrate, where the substrate is transferred from an ambient environment into a clean environment. The substrate is heated to at least a first temperature within the clean environment, and then maintained at no less than the first temperature within the clean environment. The substrate is selectively transferred within the clean environment to more than one processing chambers, and processed in the more than one processing chambers. The substrate is transferred from the clean environment into the ambient environment.

US Patent:

6969683, Nov 29, 2005

Filed:

Dec 31, 2003

Appl. No.:

10/750348

Inventors:

Rongxiang Hu - San Jose CA, US
Yongbae Kim - Cupertino CA, US
Sang-Yun Lee - Stanford CA, US
Hiroaki Takikawa - Chagasaki, JP
Shumay Dou - Saratoga CA, US
Sarah Neuman - San Mateo CA, US
Philippe Schoenborn - San Mateo CA, US
Keith Chao - Saratoga CA, US
Dilip Vijay - Foster City CA, US
Kai Zhang - Saratoga CA, US
Masaichi Eda - Gresham OR, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L021/311

US Classification:

438697, 438700, 438639

Abstract:

A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.