John A Fitzsimmons

US Patent:

7327033, Feb 5, 2008

Filed:

Aug 5, 2004

Appl. No.:

10/710828

Inventors:

Daniel C. Edelstein - White Plains NY, US
John A. Fitzsimmons - Poughkeepsie NY, US
Jeffrey P. Gambino - Westford VT, US
Anthony K. Stamper - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/52

US Classification:

257751, 257753, 257762, 257E23141

Abstract:

Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.

US Patent:

7405147, Jul 29, 2008

Filed:

Jan 30, 2004

Appl. No.:

10/707996

Inventors:

Daniel C. Edelstein - White Plains NY, US
Matthew E. Colburn - Hopewell Junction NY, US
Timothy J. Dalton - Ridgefield CT, US
John A. Fitzsimmons - Poughkeepsie NY, US
Jeffrey P. Gambino - Westford VT, US
Elbert E. Huang - Tarrytown NY, US
Michael W. Lane - Cortlandt Manor NY, US
Vincent J. McGahay - Poughkeepsie NY, US
Lee M. Nicholson - Katonah NY, US
Satyanarayana V. Nitta - Poughquag NY, US
Sampath Purushothaman - Yorktown Heights NY, US
Sujatha Sankaran - Wappingers Falls NY, US
Thomas M. Shaw - Peekskill NY, US
Andrew H. Simon - Fishkill NY, US
Anthony K. Stamper - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438618, 438623, 438703

Abstract:

A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column.

US Patent:

7592685, Sep 22, 2009

Filed:

Aug 31, 2007

Appl. No.:

11/849048

Inventors:

Daniel C. Edelstein - White Plains NY, US
Matthew E. Colburn - Hopewell Junction NY, US
Timothy J. Dalton - Ridgefield CT, US
John A. Fitzsimmons - Poughkeepsie NY, US
Jeffrey P. Gambino - Westford VT, US
Elbert E. Huang - Tarrytown NY, US
Michael W. Lane - Cortlandt Manor NY, US
Vincent J. McGahay - Poughkeepsie NY, US
Lee M. Nicholson - Katonah NY, US
Satyanarayana V. Nitta - Poughquag NY, US
Sampath Purushothaman - Yorktown Heights NY, US
Sujatha Sankaran - Wappingers Falls NY, US
Thomas M. Shaw - Peekskill NY, US
Andrew H. Simon - Fishkill NY, US
Anthony K. Stamper - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/93

US Classification:

257522, 257499

Abstract:

Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.

US Patent:

7892940, Feb 22, 2011

Filed:

Sep 6, 2007

Appl. No.:

11/851123

Inventors:

Daniel C. Edelstein - White Plains NY, US
Matthew E. Colburn - Hopewell Junction NY, US
Timothy J. Dalton - Ridgefield CT, US
John A. Fitzsimmons - Poughkeepsie NY, US
Jeffrey P. Gambino - Westford VT, US
Elbert E. Huang - Tarrytown NY, US
Michael W. Lane - Cortlandt Manor NY, US
Vincent J. McGahay - Poughkeepsie NY, US
Lee M. Nicholson - Katonah NY, US
Satyanarayana V. Nitta - Poughquag NY, US
Sampath Purushothaman - Yorktown Heights NY, US
Sujatha Sankaran - Wappingers Falls NY, US
Thomas M. Shaw - Peekskill NY, US
Andrew H. Simon - Fishkill NY, US
Anthony K. Stamper - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438421, 438618, 438703

Abstract:

Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

US Patent:

8129286, Mar 6, 2012

Filed:

Jun 16, 2008

Appl. No.:

12/139803

Inventors:

Daniel C. Edelstein - White Plains NY, US
Matthew E. Colburn - Hopewell Junction NY, US
Timothy J. Dalton - Ridgefield CT, US
John A. Fitzsimmons - Poughkeepsie NY, US
Jeffrey P. Gambino - Westford VT, US
Elbert E. Huang - Tarrytown NY, US
Michael W. Lane - Cortlandt Manor NY, US
Vincent J. McGahay - Poughkeepsie NY, US
Lee M. Nicholson - Katonah NY, US
Satyanarayana V. Nitta - Poughquag NY, US
Sampath Purushothaman - Yorktown Heights NY, US
Sujatha Sankaran - Wappingers Falls NY, US
Thomas M. Shaw - Peekskill NY, US
Andrew H. Simon - Fishkill NY, US
Anthony K. Stamper - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/302
B44C 1/22

US Classification:

438733, 438689, 438694, 438734, 438947, 216 13, 216 41, 216 58, 216 83

Abstract:

Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

US Patent:

8294270, Oct 23, 2012

Filed:

May 26, 2011

Appl. No.:

13/116622

Inventors:

Daniel C. Edelstein - White Plains NY, US
John A. Fitzsimmons - Poughkeepsie NY, US
Jeffrey P. Gambino - Westford VT, US
Anthony K. Stamper - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/52

US Classification:

257751, 257753, 257762, 257E23145

Abstract:

Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.

US Patent:

8343868, Jan 1, 2013

Filed:

Jan 12, 2011

Appl. No.:

13/005201

Inventors:

Daniel C. Edelstein - White Plains NY, US
Matthew E. Colburn - Hopewell Junction NY, US
Timothy J. Dalton - Ridgefield CT, US
John A. Fitzsimmons - Poughkeepsie NY, US
Jeffrey P. Gambino - Westford VT, US
Elbert E. Huang - Tarrytown NY, US
Michael W. Lane - Cortlandt Manor NY, US
Vincent J. McGahay - Poughkeepsie NY, US
Lee M. Nicholson - Katonah NY, US
Satyanarayana V. Nitta - Poughquag NY, US
Sampath Purushothaman - Yorktown Heights NY, US
Sujatha Sankaran - Wappingers Falls NY, US
Thomas M. Shaw - Peekskill NY, US
Andrew H. Simon - Fishkill NY, US
Anthony K. Stamper - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438643, 438703, 438618

Abstract:

Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.

US Patent:

20030210352, Nov 13, 2003

Filed:

May 9, 2002

Appl. No.:

10/142236

Inventors:

John Fitzsimmons - Massapequa Park NY, US
Denis Phillips - New York NY, US
Michael Thaw - Ocean Township NJ, US

International Classification:

H04N007/16
H04H009/00
H04N005/268

US Classification:

348/705000, 725/009000

Abstract:

A system for monitoring a selected channel signal included within a multiplex of channel signals and for transmitting a representation of the selected channel signal to a monitoring location is disclosed. The system includes a demultiplexer which receives the multiplex of channel signals and demultiplexes the selected channel signal in response to a channel select command. A transmitter unit receives the demultiplexed channel signal from the demultiplexer, compresses the demultiplexed channel signal, converts the compressed demultiplexed channel signal to a packet signal and transmits the packet signal to the monitoring location via a telecommunications link.

Author:

John Fitzsimmons

ISBN #:

0830644865

Author:

John C. Fitzsimmons

ISBN #:

0070609918