Eun S Lee

US Patent:

D597248, Jul 28, 2009

Filed:

Sep 25, 2008

Appl. No.:

29/325133

Inventors:

Eun Ju Lee - New York NY, US
Mark W. Morton - Bronxville NY, US
Michael Castelli - West Slip NY, US

Assignee:

Bank of America Corporation - Charlotte NC

International Classification:

2699

US Classification:

D26122

US Patent:

D601296, Sep 29, 2009

Filed:

May 6, 2009

Appl. No.:

29/336608

Inventors:

Eun Ju Lee - New York NY, US
Mark W. Morton - Bronxville NY, US
Michael Castelli - West Slip NY, US

Assignee:

Bank of America Corporation - Charlotte NC

International Classification:

2699

US Classification:

D26122

US Patent:

D601297, Sep 29, 2009

Filed:

May 6, 2009

Appl. No.:

29/336611

Inventors:

Eun Ju Lee - New York NY, US
Mark W. Morton - Bronxville NY, US
Michael Castelli - West Slip NY, US

Assignee:

Bank of America Corporation - Charlotte NC

International Classification:

2699

US Classification:

D26122

US Patent:

20210208847, Jul 8, 2021

Filed:

Jan 8, 2020

Appl. No.:

16/737440

Inventors:

- Armonk NY, US
Seyoung Kim - White Plains NY, US
Eun Kyung Lee - Bedford Corners NY, US

International Classification:

G06F 7/523
G06F 7/50
G06N 3/08

Abstract:

A system is provided for error resiliency in a bit serial computation. A delay monitor enforces an overall processing duration threshold for bit-serial processing all iterations for the bit serial computation, while determining a threshold for processing each iteration. At least some iterations correspond to a respective bit in an input bit sequence. A clock generator generates a clock signal for controlling a performance of the iterations. Each of iteration units perform a particular iteration, starting with a Most Significant Bit (MSB) of the input bit sequence and continuing in descending bit significant order, and by selectively increasing the threshold for at least one iteration while skipping from processing at least one subsequent iteration whose iteration-level processing duration exceeds a remaining amount of an overall processing duration for all iterations, responsive to the at least one iteration requiring more time to complete than a current value of the threshold.

US Patent:

20170277564, Sep 28, 2017

Filed:

Mar 25, 2016

Appl. No.:

15/080689

Inventors:

- Armonk NY, US
Eun Kyung Lee - Elmsford NY, US
Yoonho Park - Chappaqua NY, US

International Classification:

G06F 9/48
G06F 9/50

Abstract:

A method, apparatus, and computer program product are provided for thermal- and spatial-aware task scheduling. The method may include monitoring a temperature for each core of a central processing unit having a plurality of cores; determining, from the monitoring, a set of hotspot cores from the plurality of cores determining temperature information and distance information for each hotspot core in the set of hotspot cores relative to each of the other cores on the central processing unit; calculating a placement metric for each core of the central processing unit based at least on the determined distance information and the determined temperature information; and scheduling a task by allocating the task to one or more cores of the central processing unit according to the placement metric.

Author:

Eun Lee

ISBN #:

8952744896

Author:

Eun Lee

ISBN #:

8952747135

Author:

Eun Lee

ISBN #:

8952748697

Author:

Eun Lee

ISBN #:

8952748816

Author:

Eun Koo Lee

ISBN #:

3631500386

Author:

Eun Sul Lee

ISBN #:

0122622707

Author:

Eun Sul Lee

ISBN #:

0123694922

Author:

Eun Sul Lee

ISBN #:

0803930143