David Ralph Larsen

US Patent:

7062598, Jun 13, 2006

Filed:

Apr 29, 2003

Appl. No.:

10/425573

Inventors:

Peter D. Lapidus - Boulder CO, US
David H. Larsen - Boulder CO, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711102, 714710

Abstract:

A processing system comprising: i) a read-only memory (ROM) that stores original ROM code; ii) a custom array that stores replacement ROM code; and iii) control logic that receives an incoming ROM address and a read request signal generated by a source device. The control logic, in response to receipt of the incoming ROM address and the read request signal, compares the incoming ROM address to a patched address associated with the ROM. If a match occurs, the control logic outputs to the custom array a translated address associated with the patched address. The custom array then outputs a first line of replacement ROM code associated with the translated address.

US Patent:

8095331, Jan 10, 2012

Filed:

Nov 26, 2008

Appl. No.:

12/324212

Inventors:

Christian Haufe - Dresden, DE
Ingo Kuehn - Dresden, DE
David Larsen - Boulder CO, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

G01R 31/00
G06F 17/50

US Classification:

702117, 716106

Abstract:

In a transaction-based verification environment for complex semiconductor devices, enhanced verification efficiency may be achieved by providing a transaction to machine code translator and an appropriate interface that enables access of the translated machine code instruction by a CPU under test. In this manner, transaction-based test environments may have a high degree of re-usability and may be used for verification on block level and system level.

US Patent:

20090144012, Jun 4, 2009

Filed:

May 16, 2008

Appl. No.:

12/122017

Inventors:

Christian Haufe - Dresden, DE
Ingo Kuehn - Dresden, DE
David Larsen - Boulder CO, US

International Classification:

G01R 31/00

US Classification:

702117

Abstract:

In a transaction-based verification environment for complex semiconductor devices, enhanced verification efficiency may be achieved by providing a transaction to machine code translator and an appropriate interface that enables access of the translated machine code instruction by a CPU under test. In this manner, transaction-based test environments may have a high degree of reusability and may be used for verification on block level and system level.

Author:

David G. Larsen

ISBN #:

0672214474

Author:

David G. Larsen

ISBN #:

0672215462

Author:

David G. Larsen

ISBN #:

0672215500

Author:

David G. Larsen

ISBN #:

0672215519

Author:

David G. Larsen

ISBN #:

0672216337

Author:

David G. Larsen

ISBN #:

0672216973

Author:

David G. Larsen

ISBN #:

0672217392

Author:

David G. Larsen

ISBN #:

0672218623