Armando Garcia

Author:

Armando Ramos Garcia

ISBN #:

8424125207

Author:

Armando Grana Garcia

ISBN #:

8460443663

Author:

Armando Grana Garcia

ISBN #:

8479250151

US Patent:

55881220, Dec 24, 1996

Filed:

Jun 15, 1994

Appl. No.:

8/260107

Inventors:

Armando Garcia - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1516

US Classification:

395250

Abstract:

A universal buffered interface (UBIF 34) couples a local bus (32) to a global bus (24) and supports, on the local bus, up to four nodes. The nodes may be comprised of processors (22a, 28a), memory banks, and/or I/O interfaces. Each processor has an associated private memory. The UBIF includes bidirectional, first-in-first-out (FIFO) buffers, or queues, for each node and operates in conjunction with a two-level bus hierarchy. The UBIF supports decoupled global memory (26) read requests and replies, supports decoupled, atomic read-modify-write operations to Global Memory, and block-read support for transferring contiguous blocks of global memory to processors or I/O interfaces. The UBIF also enables the use of an inter-processor communication (IPC) mechanism that enables any processor to send an interrupt to any other processor or processors in the system during a single global bus cycle. An interrupt mask is transferred over the address bus during a specially marked bus cycle, the interrupt mask identifying the processor or processors to be interrupted.

US Patent:

52805913, Jan 18, 1994

Filed:

Jul 22, 1991

Appl. No.:

7/733563

Inventors:

Armando Garcia - Yorktown Heights NY
Curtis S. McDowell - Thornwood NY

Assignee:

International Business Machines, Corporation - Armonk NY

International Classification:

G06F 13364

US Classification:

395325

Abstract:

An Arbiter (36) is coupled to a multiprocessor system (10) Global Bus (24) having two separate main buses: an address bus (ABUS) and a data bus (DBUS). Bus agents coupled to the Global Bus request access to use the buses by asserting bus request lines to the Arbiter. The Arbiter is a dual level, round robin Arbiter that employs a fast, single-cycle arbitration technique. During each system clock cycle, the Arbiter considers the signals on the request input lines and generates corresponding grant output lines which dictate, for the next cycle, which bus agent is to receive access to the address bus and which bus agent is to receive access to the data bus.

US Patent:

54695422, Nov 21, 1995

Filed:

Jul 22, 1991

Appl. No.:

7/733767

Inventors:

David J. Foster - White Plains NY
Armando Garcia - Yorktown Heights NY
Robert B. Pearson - Cold Spring NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300
G06F 1100

US Classification:

39520001

Abstract:

Apparatus and method for use in a multiprocessor system (10) having a plurality of processing nodes (P0-P3) each of which includes a local data processor (22a, 28a). The apparatus includes an interface (42) to a controller (14), the interface including a register (48) for storing a function received from the controller, such as a diagnostic function. The interface further includes circuitry (50) for providing the diagnostic function as a packet to an input terminal of a bit serial communication bus (40). The communication bus is threaded through each of the plurality of processing nodes and has an output terminal that terminates at the interface. Each of the nodes includes a register (54) for receiving the packet and, responsive to information conveyed thereby, for halting the local data processor and for controlling the operation of local data processor control signal lines, data signal lines, and address signal lines so as to execute the diagnostic function, such as reading data from or writing data to a specified location. The local data processor may also be reset, rebooted, restarted from a halted condition, or interrupted.

US Patent:

62020978, Mar 13, 2001

Filed:

Jan 17, 1995

Appl. No.:

8/373052

Inventors:

David James Foster - White Plains NY
Armando Garcia - Yorktown Heights NY
Robert Bernard Pearson - Cold Spring NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15173

US Classification:

709238

Abstract:

Apparatus and method for use in a multiprocessor system (10) having a plurality of processing nodes (P0-P3) each of which includes a local data processor (22a, 28a). The apparatus includes an interface (42) to a controller (14), the interface including a register (48) for storing a function received from the controller, such as a diagnostic function. The interface further includes circuitry (50) for providing the diagnostic function as a packet to an input terminal of a bit serial communication bus (40). The communication bus is threaded through each of the plurality of processing nodes and has an output terminal that terminates at the interface. Each of the nodes includes a register (54) for receiving the packet and, responsive to information conveyed thereby, for halting the local data processor and for controlling the operation of local data processor control signal lines, data signal lines, and address signal lines so as to execute the diagnostic function, such as reading data from or writing data to a specified location. The local data processor may also be reset, rebooted, restarted from a halted condition, or interrupted.

US Patent:

53275705, Jul 5, 1994

Filed:

Jul 22, 1991

Appl. No.:

7/734432

Inventors:

David J. Foster - White Plains NY
Armando Garcia - Yorktown Heights NY
Robert B. Pearson - Cold Spring NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

395800

Abstract:

A multiprocessor data processing system (10), and a method of operating same, so as to provide efficient bandwidth utilization of shared system resources (24, 26). The system includes a plurality of processor nodes, each of which includes a data processor (22a, 28a). A first step of a method buffers data written by a data processor to a first bus (23a), prior to the data being transmitted to a second bus (32). Also buffered are byte enable (BE) signals generated by the data processor in conjunction with the data written by the data processor. A next step performs a main memory (26) write operation by transmitting the buffered data to the second bus; responsive to the stored BE signals, also transmitting a control signal for indicating if a memory write is to be accomplished as a read-modify-write (RMW) type of memory operation; and transmitting the stored BE signals to the second bus. A further step couples the data, the RMW signal, and the BE signals from the second bus to a third bus (24) for reception by the main memory.

US Patent:

58705724, Feb 9, 1999

Filed:

Dec 23, 1996

Appl. No.:

8/798186

Inventors:

Armando Garcia - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1516

US Classification:

395309

Abstract:

A multiprocessor data processing system includes a group of computational data processor nodes including at least one communication data processor node, at least one shared global memory with memory banks, and a number of bus interfaces each coupled between one of a set of local buses and a global bus. Each interface includes a number of input queues and output queues coupled between the local bus and the global bus. The interface supports the use of an inter-processor communication (IPC) mechanism that allows any processor to send an interrupt to any other processor in the system during a single global bus cycle. An interrupt mask is transferred over the address bus during a specially marked bus cycle, with the interrupt mask identifying the processor or processors to be interrupted for interprocessor communication.

US Patent:

54106540, Apr 25, 1995

Filed:

Jul 22, 1991

Appl. No.:

7/733517

Inventors:

David J. Foster - White Plains NY
Armando Garcia - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1502

US Classification:

395275

Abstract:

Interface circuitry for coupling to a microprocessor device. The interface circuitry includes an input for receiving address signal lines and control signal lines generated by the microprocessor device. The interface further includes an address decoder, responsive to the received address signal lines, for determining if a microprocessor-generated memory access is directed to a private memory, accessible only by the microprocessor device, or to a shared memory that is accessible by a plurality of microprocessor devices. Responsive to the address decoder, the interface circuitry provides first address signal lines and first control signal lines to the private memory in response to the microprocessor device generating a memory access to the private memory. Also responsive to the address decoder, the interface circuitry provides second address signal lines and second control signal lines for coupling to the shared memory in response to the microprocessor device generating a memory access to the shared memory. The interface circuitry further includes interrupt control circuitry, inter-processor interrupt circuitry, DMA circuitry, a serial bus interface, and also provides a plurality of miscellaneous functions for the microprocessor.