Zhiguo Sun

US Patent:

20100038793, Feb 18, 2010

Filed:

Aug 12, 2008

Appl. No.:

12/190131

Inventors:

Griselda Bonilla - Fishkill NY, US
Tien Cheng - Bedford NY, US
Lawrence A. Clevenger - LaGrangeville NY, US
Stephan Grunow - Poughkeepsie NY, US
Chao-Kun Hu - Somers NY, US
Roger A. Quon - Rhinebeck NY, US
Zhiguo Sun - Beacon NY, US
Yiheng Xu - Hopewell Junction NY, US
Yun Wang - Poughquag NY, US

Assignee:

International Business Machines Corporation - Armonk NY
Samsung Electronics Co., LTD - Gyeonggi-Do
Chartered Semiconductor Manufacturing LTD. - Singapore

International Classification:

H01L 23/48

US Classification:

257762, 438618, 257E23011

Abstract:

Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiCNHdisposed upon the conductive interconnect; a second capping layer comprising SiCNH(has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiCNHdisposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.

US Patent:

20200388693, Dec 10, 2020

Filed:

Jun 10, 2019

Appl. No.:

16/435563

Inventors:

- Grand Cayman, KY
ZHIGUO SUN - Halfmoon NY, US
GUOLIANG ZHU - Rexford NY, US
XINYUAN DOU - Clifton Park NY, US

International Classification:

H01L 29/51
H01L 29/78
H01L 29/66
H01L 21/02

Abstract:

A semiconductor device is provided, which includes providing an active region, a source region, a drain region, a dielectric layer, a gate structure and a nitrogen-infused dielectric layer. The source region and the drain region are formed in the active region. The dielectric layer is disposed over the source region and the drain region. The gate structure formed in the dielectric layer is positioned between the source region and the drain region. The nitrogen-infused dielectric layer is disposed over the dielectric layer and over the gate structure.

US Patent:

20200219763, Jul 9, 2020

Filed:

Jan 9, 2019

Appl. No.:

16/244071

Inventors:

- Grand Cayman, KY
RAVI PRAKASH SRIVASTAVA - Clifton Park NY, US
ZHIGUO SUN - Halfmoon NY, US
QIANG FANG - Ballston Lake NY, US
CHENG XU - Dresden, DE
GUOXIANG NING - Clifton Park NY, US

International Classification:

H01L 21/768
H01L 23/522
H01L 21/311

Abstract:

A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer having a conductive line and depositing a first aluminum-containing layer over the interconnect layer. A dielectric layer is deposited over the first aluminum-containing layer, followed by a second aluminum-containing layer deposited over the dielectric layer. A via opening is formed in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.

US Patent:

20190318931, Oct 17, 2019

Filed:

Apr 11, 2018

Appl. No.:

15/950364

Inventors:

- Grand Cayman, KY
Xiaohan Wang - Clifton Park NY, US
Qiang Fang - Ballston Lake NY, US
Zhiguo Sun - Halfmoon NY, US
Jinping Liu - Ballston Lake NY, US
Hui Zang - Guilderland NY, US

International Classification:

H01L 21/033
H01L 21/768
H01L 23/528
H01L 23/522

Abstract:

Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning. A mandrel line is patterned from a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer of the mandrel line is removed to expose a first section of the first mandrel layer. The first section of the first mandrel layer is masked, and the second sections of the second mandrel layer and the underlying second portions of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with an etching process to form a trench in the hardmask. A second portion of the hardmask is masked by the first portion of the first mandrel layer during the etching process to form a cut in the trench.

US Patent:

20190206729, Jul 4, 2019

Filed:

Jan 2, 2018

Appl. No.:

15/860318

Inventors:

- GRAND CAYMAN, KY
Shafaat AHMED - Ballston Lake NY, US
Zhiguo SUN - Halfmoon NY, US
Jiehui SHU - Clifton Park NY, US
Dinesh R. KOLI - Halfmoon NY, US
Wei-Tsu TSENG - Hopewell Junction NY, US

International Classification:

H01L 21/768
H01L 23/522
H01L 23/532

Abstract:

The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.

US Patent:

20180166383, Jun 14, 2018

Filed:

Dec 13, 2016

Appl. No.:

15/377592

Inventors:

- Grand Cayman, KY
Zhiguo SUN - Halfmoon NY, US
Moosung M. CHAE - Englewood Cliffs NJ, US

International Classification:

H01L 23/528
H01L 23/532
H01L 21/768

Abstract:

The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The structure includes: a plurality of metal lines formed on an insulator layer; and a dielectric material completely filling a space having a first dimension between metal lines of the plurality of metal lines and providing a uniform airgap with a space having a second dimension between metal lines of the plurality of metal lines. The first dimension is larger than the second dimension.

US Patent:

20170287777, Oct 5, 2017

Filed:

Apr 5, 2016

Appl. No.:

15/091138

Inventors:

- Grand Cayman, KY
Zhiguo Sun - Halfmoon NY, US
Keith Tabakman - Gansevoort NY, US

International Classification:

H01L 21/768
H01L 29/417
H01L 29/66

Abstract:

One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening.

US Patent:

20160365277, Dec 15, 2016

Filed:

Jun 15, 2015

Appl. No.:

14/740035

Inventors:

- Grand Cayman KY, US
Zhiguo SUN - Halfmoon NY, US
Jiehui SHU - Clifton Park NY, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman

International Classification:

H01L 21/768
H01L 23/522
H01L 23/532

Abstract:

A starting metallization structure for electrically coupling one or more underlying semiconductor devices, the structure including a bottom layer of dielectric material with metal-filled via(s) situated therein, a protective layer over the bottom layer, and a top layer of dielectric material over the protective layer. A sacrificial layer of amorphous silicon is formed over the top layer of dielectric material, a protective layer is formed over the sacrificial layer and via(s) through each layer above the metal-filled via(s) to expose the metal of the metal-filled via(s). The protective layer is then selectively removed, as well as the sacrificial layer of amorphous silicon.