Zhigang Living Wang

US Patent:

6469939, Oct 22, 2002

Filed:

Oct 1, 2001

Appl. No.:

09/969572

Inventors:

Zhigang Wang - San Jose CA
Richard Fastow - Cupertino CA
Sameer S. Haddad - San Jose CA
Chi Chang - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518528, 36518533

Abstract:

A source resistor or a positive voltage is coupled to the source and a negative bias voltage is applied at the substrate or p-well of flash memory cells for enhanced efficiency during programming and/or during an APDE (Automatic Program Disturb after Erase) process for a flash memory device. Furthermore, in a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected.

US Patent:

6472236, Oct 29, 2002

Filed:

Jul 13, 2001

Appl. No.:

09/904740

Inventors:

Zhigang Wang - San Jose CA
Nian Yang - San Jose CA
Tien-Chun Yang - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2166

US Classification:

438 14, 438216, 438275

Abstract:

System and method for determining a respective effective oxide thickness for each of first and second dielectric structures that form a MOS (metal oxide semiconductor) stack. A first plurality of test MOS (metal oxide semiconductor) stacks are formed, and each test MOS stack includes a respective first dielectric structure comprised of a first dielectric material and a respective second dielectric structure comprised of a second dielectric material. A respective deposition time for forming the respective first dielectric structure corresponding to each of the first plurality of test MOS stacks is varied such that a respective first effective oxide thickness of the respective first dielectric structure varies for the first plurality of test MOS stacks. A respective second effective oxide thickness of the respective second dielectric structure is maintained to be substantially same for each of the first plurality of test MOS stacks. A respective total effective oxide thickness, EOT , is measured for each of the first plurality of test MOS stacks.

US Patent:

6486682, Nov 26, 2002

Filed:

Jul 13, 2001

Appl. No.:

09/904736

Inventors:

Zhigang Wang - San Jose CA
Nian Yang - San Jose CA
Tien-Chun Yang - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2358

US Classification:

324671, 324769, 324765, 438591, 438216, 438261, 438287, 438782

Abstract:

First and second dielectric constants, e and e respectively, for first and second dielectric materials forming a MOS (metal oxide semiconductor) stack are determined. First and second test MOS stacks having first and second total effective oxide thickness, EOT and EOT , respectively, are formed. The first and second test MOS stacks include first and second interfacial structures comprised of the second dielectric material with first and second thickness, T and T , respectively. In addition, the first and second test MOS stacks include first and second high-K structures comprised of the first dielectric material with first and second thickness, T and T , respectively. The thickness parameters EOT , T , T , EOT , T , and T of the test MOS stacks are measured. The dielectric constants, e and e , are then determined depending on relations between values of EOT , T , and T , and between values of EOT , T , and T.

US Patent:

6510085, Jan 21, 2003

Filed:

May 18, 2001

Appl. No.:

09/861031

Inventors:

Richard Fastow - Cupertino CA
Zhigang Wang - San Jose CA
Sameer Haddad - San Jose CA
Chi Chang - Redwood City CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518528, 36518526, 36518533

Abstract:

Methods of programming and soft programming short channel NOR flash memory cells that reduce the programming currents and column leakages during both programming and soft programming while maintaining fast programming speeds. During programming, a voltage of between 7 and 10 volts is applied to the control gate, a voltage of between 4 and 6 volts; is applied to the drain, a voltage of between 0. 5 and 2. 0 volts is applied to the source and a voltage of between minus 2 and minus 0. 5 volts is applied to the substrate of the selected cell to be programmed. During soft programming, a voltage of between 0. 5 and 4. 5 volts is applied to the control gates, between 4 and 5. 5 volts is applied to the drains, between 0. 5 and 2 volts is applied to the sources and between minus 2. 0 and minus 0.

US Patent:

6541338, Apr 1, 2003

Filed:

Jul 30, 2001

Appl. No.:

09/917182

Inventors:

Zhigang Wang - San Jose CA
Richard Fastow - Cupertino CA

Assignee:

Advanced Micro Devices Inc. - Sunnyvale CA

International Classification:

H01L 218247

US Classification:

438258, 438264, 438529

Abstract:

A method of forming flash memory EEPROM devices having a low energy source implant and a high-energy V connection implant such that the intrinsic source defect density is reduced and the V resistance is low. The source regions are implanted with a low energy, low dosage dopant ions and the V regions are implanted with a high energy, high dosage dopant ions.

US Patent:

6570787, May 27, 2003

Filed:

Apr 19, 2002

Appl. No.:

10/126330

Inventors:

Zhigang Wang - Santa Clara CA
Nian Yang - San Jose CA
Xin Guo - Mountain View CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518517, 36518518, 36518533

Abstract:

The present invention relates to a flash memory array architecture comprising a plurality of flash memory cells arranged in a NOR type array configuration. Each of the plurality of flash memory cells have a source terminal coupled together to form a common source. The array architecture further comprises a common source selection component coupled between the common source of the array and a predetermined potential. The common source selection component is operable to couple the common source to the predetermined potential in a first state and electrically isolate or float the common source from the predetermined potential in a second state, thereby reducing leakage of non-selected cells associated with the activated bit line during a program mode of operation.

US Patent:

6576487, Jun 10, 2003

Filed:

Apr 19, 2002

Appl. No.:

10/126363

Inventors:

Zhigang Wang - San Jose CA
Harpreet Kaur Sachar - Sunnyvale CA
Kuo-Tung Chang - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G01R 3126

US Classification:

438 17, 438 14, 438424

Abstract:

The present invention details a method which characterizes an STI fabrication process, and more particularly provides information relating to a variation in the STI sidewall profile between trenches in a middle portion of an array and a trench on an outer portion thereof. The method comprises forming two STI arrays with an STI fabrication process, forming a conductive layer over each array, biasing each conductive layer and determining a current associated therewith. The two current are then utilized to ascertain the variation of interest.

US Patent:

6590260, Jul 8, 2003

Filed:

Mar 20, 2002

Appl. No.:

10/103077

Inventors:

Nian Yang - San Jose CA
John Jianshi Wang - San Jose CA
Zhigang Wang - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2976

US Classification:

257347, 257368, 257296

Abstract:

A method for enhancing the operating characteristics of memory devices ( C), such as flash memory devices, by manipulating the Fermi energy levels of the substrate ( ) and the floating gate ( ). In so doing, the gap between the minimum conduction band energy level ( ) and the Fermi energy level ( ) of the floating gate ( ) is extended so as to readily facilitate the movement of electrons from the substrate ( ) into the floating gate ( ).

Author:

Zhigang Wang

ISBN #:

7503604018