Yutaka Tr Hori from 879 S Sapphire Ln, Anaheim, CA 92807, age 64, Phone: 408 718-7437

Master/Slave Mode For Sensor Processing Devices
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US Patent:

7848825, Dec 7, 2010
Filed:

Jan 3, 2007
Appl. No.:

11/650042
Inventors:

Thomas James Wilson - Pleasanton CA, US
Yutaka Hori - Cupertino CA, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G05B 19/18
US Classification:

700 3, 700 20, 345173
Abstract:

A computer system having two or more controllers operating in a Master/Slave configuration is disclosed. In one embodiment, the computer system includes: a sensor panel having a first portion for generating a first set of sense signals indicative of a touch or no-touch condition on the first portion, and a second portion for generating a second set of sense signals indicative of a touch or no-touch condition on the second portion; a first device for receiving and processing the first set of output signals from the first portion of the panel; and a second device for receiving and processing the second set of output signals from the second portion of the panel, wherein the first and second devices operate cooperatively in a Master/Slave configuration.

Method To Compensate For The Frequency Dependence Of Sense Signal Preprocessing
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US Patent:

8363021, Jan 29, 2013
Filed:

Sep 11, 2009
Appl. No.:

12/558397
Inventors:

Christoph Horst Krah - Los Altos CA, US
Yutaka Hori - Cupertino CA, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G06F 3/041
US Classification:

345173, 345174, 345204, 345214
Abstract:

Compensating for the frequency dependence of sense signal preprocessing in preprocessing channel circuitry is provided. The frequency dependence of the preprocessing channels can be modified to change a frequency dependent channel into a frequency independent channel, to change a frequency independent channel into a frequency dependent channel, or to change the frequency dependency characteristics of a frequency dependent channel. Modification of frequency dependency may be accomplished, for example, by modifying certain parameters of a preprocessing channel's components, which can include components for amplifying, filtering, phase adjusting, demodulating, decrypting, for example. A pipelined process may be used to modify the frequency dependency of multiple channels. Compensating for frequency dependencies can have multiple advantages, such as reduction of memory requirements and DIE size.

Memory Access Without Internal Microprocessor Intervention
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US Patent:

8510481, Aug 13, 2013
Filed:

Jan 3, 2007
Appl. No.:

11/650118
Inventors:

Thomas James Wilson - Pleasanton CA, US
Yutaka Hori - Cupertino CA, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G06F 13/28
US Classification:

710 22, 710 23, 710 24, 710 25, 710 26, 710 27, 710 28
Abstract:

A method and system for accessing a computer system memory without processor intervention is disclosed. In one embodiment, the method includes initiating a predetermined communication protocol between a first device and a second device, the first device including a first processor, a first memory and a first communication interface, the second device including a second processor, a second memory and a second communication interface. The predetermined communication protocol enables an access operation to be performed on the first or second memory without intervention by the first or second processor. In one embodiment, the predetermined communication protocol utilizes a plurality of predefined packet types which are identified by a packet header decoder.

Low Power Digital Interface
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US Patent:

8510485, Aug 13, 2013
Filed:

Nov 29, 2007
Appl. No.:

11/947723
Inventors:

Thomas James Wilson - Pleasanton CA, US
Yutaka Hori - Cupertino CA, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G06F 3/00
G06F 5/00
US Classification:

710 61, 710 52, 710 53, 710 54, 710 55, 710 56, 710 57, 710 58, 710 59, 710 60
Abstract:

This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.

Internal Memory Mapped External Memory Interface
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US Patent:

20090138673, May 28, 2009
Filed:

Nov 28, 2007
Appl. No.:

11/946811
Inventors:

Thomas James WILSON - Pleasanton CA, US
Yutaka Hori - Cupertino CA, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G06F 12/00
US Classification:

711211, 711E12001
Abstract:

This is directed to allowing a processor of a device to use ordinary internal memory read and write instructions that read and write to external memory. Thus, the complexities associated with the existing methods of accessing external memory can be avoided. More specifically, an address space portion that does not correspond to any existing internal memory can be defined as associated with an external memory. When access to the external memory is required, the processor can simply issue ordinary internal memory read/write instructions that are addressed to the above mentioned address space. An interface controller can receive the read and write instructions and communicate with an external memory in order to execute them. The controller can then send a result back to the processor (if required) in the format that would be expected from an internal memory access operation.

Multiplexing Multiple Serial Interfaces
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US Patent:

20140211817, Jul 31, 2014
Filed:

Jan 31, 2013
Appl. No.:

13/756222
Inventors:

- Cupertino CA, US
Yutaka Hori - Cupertino CA, US
Assignee:

APPLE INC. - Cupertino CA
International Classification:

H04L 12/56
US Classification:

370542
Abstract:

An integrated circuit with two operating modes is described. During a first operating mode, a de-multiplexer selectively couples information received via a common set of pads to first control logic, which decodes the information based on a first serial-interface technique. Moreover, during a second operating mode, the de-multiplexer selectively couples a first portion of the information to the first control logic and a second portion of the information to second control logic, which decodes the second portion based on a second serial-interface technique. By facilitating time-domain de-multiplexing of two similar serial-interface techniques, the integrated circuit can overcome the constraints imposed by a low or limited pin count.