Yun Wu

US Patent:

6912163, Jun 28, 2005

Filed:

Sep 9, 2003

Appl. No.:

10/658506

Inventors:

Wei Zheng - Santa Clara CA, US
Yun Wu - Sunnyvale CA, US
Hidehiko Shiraiwa - San Jose CA, US
Mark T. Ramsbey - Sunnyvale CA, US
Tazrien Kamal - San Jose CA, US

Assignee:

FASL, LLC - Sunnyvale CA

International Classification:

G11C016/04

US Classification:

36518529, 36518518

Abstract:

A charge trapping dielectric memory device. The memory device includes a gate electrode disposed over a dielectric stack that includes a dielectric charge trapping layer. The gate electrode has a work function of about 4. 6 eV to about 5. 2 eV.

US Patent:

7163860, Jan 16, 2007

Filed:

May 6, 2003

Appl. No.:

10/430471

Inventors:

Tazrien Kamal - San Jose CA, US
Yun Wu - Sunnyvale CA, US
Mark Ramsbey - Sunnyvale CA, US
Jean Yee-Mei Yang - Sunnyvale CA, US
Arvind Halliyal - Cupertino CA, US
Rinji Sugino - San Jose CA, US
Hidehiko Shiraiwa - San Jose CA, US
Fred T K Cheung - San Jose CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 21/8247

US Classification:

438257, 438954, 257E2118

Abstract:

The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.

US Patent:

8299564, Oct 30, 2012

Filed:

Sep 14, 2009

Appl. No.:

12/559457

Inventors:

Yun Wu - San Jose CA, US
Bei Zhu - Los Gatos CA, US
Zhiyuan Wu - San Jose CA, US
Michael J. Hart - Palo Alto CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 21/336
H01L 21/8234

US Classification:

257509, 257499, 257500, 257183, 257192, 257200, 257201, 438700, 438743

Abstract:

Formation of transistors, such as, e. g. , PMOS transistors, with diffusion regions having different depths for equalization of performance among transistors of an integrated circuit is described. Shallow-trench isolation structures are formed in a substrate formed at least in part of silicon for providing the transistors with at least substantially equivalent channel widths and lengths. A series of masks and etches is performed to form first recesses and second recesses defined in the silicon having different depths and respectively associated with first and second transistors. The second recesses are deeper than the first recesses. A silicon germanium film is formed in the first recesses and the second recesses. The silicon germanium film in the second recesses is thicker than the silicon germanium film in the first recesses, in order to increase performance of the second transistor so it is closer to the performance of the first transistor.

US Patent:

8350253, Jan 8, 2013

Filed:

Jan 29, 2010

Appl. No.:

12/697027

Inventors:

Bei Zhu - Los Gatos CA, US
Bang-Thu Nguyen - Santa Clara CA, US
Qi Lin - Cupertino CA, US
Zhiyuan Wu - San Jose CA, US
Ping-Chin Yeh - San Jose CA, US
Yun Wu - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 29/06

US Classification:

257 19, 257E29193

Abstract:

An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.

US Patent:

8350365, Jan 8, 2013

Filed:

Jan 13, 2011

Appl. No.:

13/005680

Inventors:

Yun Wu - San Jose CA, US
Qi Lin - Cupertino CA, US
Bang-Thu Nguyen - Santa Clara CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 21/4763

US Classification:

257632, 257635, 257638, 257E21495, 438510, 438514, 438942

Abstract:

A hard implantation mask layer is formed on a semiconductor wafer. An etch mask layer is formed on the hard implantation mask layer and patterned. The hard implantation mask layer is etched to form a well implantation pattern and ions are implanted into the semiconductor wafer to form wells in the semiconductor wafer, in areas where the semiconductor wafer is not covered by the well implantation mask.

US Patent:

20090248753, Oct 1, 2009

Filed:

Jan 3, 2008

Appl. No.:

11/968653

Inventors:

Kevin Tsai - Oakland CA, US
Bob Ham - Atlanta GA, US
Yun Wu - New York NY, US
Dwayne Lanclos - Euless TX, US
Venkata Raj Pochiraju - Bloomingdale IL, US

Assignee:

MICROSOFT CORPORATION - Redmond WA

International Classification:

G06F 12/00
G06F 17/30
G06F 12/16

US Classification:

707202, 707200, 707 7, 707E17005, 707E17044

Abstract:

A method of evaluating an implementation of a DBMS is provided. The method comprises collecting data associated with the implementation of the DBMS and accessing a database comprising problems and their associated solutions, wherein the solutions are configured to remedy at least one of the problems. The method further comprises comparing the data associated with the implementation of the DBMS with the problems and identifying at least one problem associated with the DBMS. Finally, a DBMS risk assessment report is generated that identifies the problem associated with the DBMS and a solution configured to remedy the problem.

US Patent:

20210410228, Dec 30, 2021

Filed:

Jun 23, 2021

Appl. No.:

17/355379

Inventors:

- Suwanee GA, US
Inigo Arockia Nirmal Nevis - Sunnyvale CA, US
Yun Wu - Sunnyvale CA, US
Tyan-Shu Jou - Sunnyvale CA, US

Assignee:

ARRIS Enterprises LLC - Suwanee GA

International Classification:

H04W 88/08
H04W 88/10
H04W 40/12
H04W 74/00
H04W 84/18

Abstract:

During operation, a mesh network access point (MAP) may communicate, via multiple mesh paths in a mesh network with the one or more root access points (RAPs), uplink packets or frames to or from at least two electronic devices. Notably, at a given time, the MAP uses a first mesh path in the mesh paths to communicate a first subset of the uplink packets or frames associated with a first electronic device in the two electronic devices and uses a second (different) mesh path in the mesh paths to communicate a second subset of the uplink packets or frames associated with a second electronic device in the two electronic devices. Moreover, the MAP may dynamically distribute the first electronic device or the second electronic device over the multiple mesh paths, e.g., based at least in part on one or more communication-performance metrics of the mesh paths and/or the mesh network.

US Patent:

20190379602, Dec 12, 2019

Filed:

Aug 23, 2019

Appl. No.:

16/549791

Inventors:

- Suwanee GA, US
Yun Wu - Sunnyvale CA, US
Gun Li - Shenzhen, CN
Ta-Chien Lin - MoInlyche, SE
Yong Seok Joo - San Jose CA, US

International Classification:

H04L 12/741
H04L 29/12
H04L 12/46

Abstract:

An access point that provides link aggregation is described. During operation, this access point receives a message that may include a Dynamic Host Configuration Protocol (DHCP) response with an Internet protocol (IP) address of a gateway for an electronic device to access a network and a media access control (MAC) address of the electronic device. Based on the MAC address and/or at least a characteristic of the electronic device (such as a configuration, a capability and/or an operating system of the electronic device), the access point may determine a different IP address of another gateway for the electronic device to access the network. Moreover, the access point may modify the DHCP response by substituting the IP address of the other gateway for the IP address of gateway in a modified DHCP response. Next, the access point provides the modified DHCP response to the electronic device.

Author:

Yun Wu

ISBN #:

7531200252

Author:

Yun Wu

ISBN #:

7806962166