Yu U Wang

US Patent:

7632733, Dec 15, 2009

Filed:

Apr 29, 2006

Appl. No.:

11/413248

Inventors:

Yu Wang - Fremont CA, US
Tiesheng Li - San Jose CA, US
Hong Chang - Cupertino CA, US

Assignee:

Alpha & Omega Semiconductor, Inc. - Sunnyvale CA

International Classification:

H01L 21/336

US Classification:

438270, 257E2153

Abstract:

This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

US Patent:

7633267, Dec 15, 2009

Filed:

Jul 5, 2005

Appl. No.:

11/175555

Inventors:

Keith Douglas Kepler - Belmont CA, US
Yu Wang - Foster City CA, US

Assignee:

Farasis Energy, Inc. - Hayward CA

International Classification:

H01M 10/46

US Classification:

320150

Abstract:

A high throughput combinatorial screening method and apparatus for the evaluation of electrochemical materials using a single voltage source () is disclosed wherein temperature changes arising from the application of an electrical load to a cell array () are used to evaluate the relative electrochemical efficiency of the materials comprising the array. The apparatus may include an array of electrochemical cells () that are connected to each other in parallel or in series, an electronic load () for applying a voltage or current to the electrochemical cells (), and a device (), external to the cells, for monitoring the relative temperature of each cell when the load is applied.

US Patent:

7710371, May 4, 2010

Filed:

Dec 16, 2004

Appl. No.:

11/014490

Inventors:

Ping Mei - Palo Alto CA, US
Jurgen Daniel - Mountain View CA, US
James B. Boyce - Los Altos CA, US
Jackson Ho - Palo Alto CA, US
Rachel Lau - San Jose CA, US
Yu Wang - Union City CA, US

Assignee:

Xerox Corporation - Norwalk CT

International Classification:

G09G 3/34
C25B 9/00
F04B 17/00
B41J 2/14
G02F 1/153
H04R 19/00

US Classification:

345 85, 204253, 204255, 204257, 204252, 4174131, 347 49, 359267, 359291, 381176, 381399

Abstract:

Cells can include variable volumes defined between a flexible structure, such as a polymer layer, and a support surface, with the flexible structure and support surface being attached in a first region that surrounds a second region in which they are unattached. Various adhesion structures can attach the flexible structure and the support surface. When unstretched, the flexible structure can lie in a flat position on the support surface. In response to a stretching force away from the support surface, the flexible structure can move out of the flat position, providing the variable volume. Electrodes, such as on the flexible structure, on the support surface, and over the flexible structure, can have charge levels that couple with each other and with the variable volume. A support structure can include a device layer with signal circuitry that provides a signal path between an electrode and external circuitry. One or more ducts can provide fluid communication with each cell's variable volume.

US Patent:

7928507, Apr 19, 2011

Filed:

Dec 9, 2009

Appl. No.:

12/653130

Inventors:

Yu Wang - Fremont CA, US
Tiesheng Li - San Jose CA, US
Hong Chang - Cupertino CA, US

Assignee:

Alpha & Omega Semiconductor, Inc. - Sunnyvale CA

International Classification:

H01L 29/66
H01L 29/06

US Classification:

257330, 257622, 257E2153, 257E21585

Abstract:

This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

US Patent:

7989103, Aug 2, 2011

Filed:

Jul 20, 2006

Appl. No.:

11/491218

Inventors:

Keith Douglas Kepler - Belmont CA, US
Yu Wang - Foster City CA, US

Assignee:

Farasis Energy, Inc. - Hayward CA

International Classification:

H01M 2/16
H01M 2/18

US Classification:

429142, 429249, 429251, 429252, 429254

Abstract:

A microporous separator film for electrochemical cells and a method of making such films is disclosed. The microporous separator film includes an intimate mixture of an electrically insulating matrix phase and a self-switching voltage activated conductive phase, wherein the voltage activated conductive phase provides a plurality of conductive paths from a first face of the microporous separator film to a second face of the microporous separator film. The method for making the composite microporous separator film includes the steps of forming an intimate mixture of at least an insulating matrix phase and a self-switching voltage activated phase, forming a film from the mixture, and generating pores within the film.

US Patent:

8080330, Dec 20, 2011

Filed:

May 28, 2011

Appl. No.:

13/118411

Inventors:

Keith Douglas Kepler - Belmont CA, US
Yu Wang - Foster City CA, US

Assignee:

Farasis Energy, Inc. - Hayward CA

International Classification:

H01M 2/16
H01M 2/18
B29C 44/04
B29C 47/00

US Classification:

429142, 429249, 429254, 264464, 264 451, 264 461

Abstract:

A microporous separator film for electrochemical cells and a method of making such films is disclosed. The microporous separator film includes an intimate mixture of an electrically insulating matrix phase and a self-switching voltage activated conductive phase, wherein the voltage activated conductive phase provides a plurality of conductive paths from a first face of the microporous separator film to a second face of the microporous separator film. The method for making the composite microporous separator film includes the steps of forming an intimate mixture of at least an insulating matrix phase and a self-switching voltage activated phase, forming a film from the mixture, and generating pores within the film.

US Patent:

8193061, Jun 5, 2012

Filed:

Apr 18, 2011

Appl. No.:

13/066583

Inventors:

Yu Wang - Fremont CA, US
Tiesheng Li - San Jose CA, US
Hong Chang - Cupertino CA, US

Assignee:

Alpha & Omega Semiconductor Incorporated - Sunnyvale CA

International Classification:

H01L 21/336

US Classification:

438270, 257E2153

Abstract:

This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

US Patent:

8471368, Jun 25, 2013

Filed:

Mar 27, 2012

Appl. No.:

13/431551

Inventors:

Yu Wang - Fremont CA, US
Tiesheng Li - San Jose CA, US
Hong Chang - Cupertino CA, US

Assignee:

Alpha and Omega Semiconductor Incorporated - Sunnyvale CA

International Classification:

H01L 29/06

US Classification:

257622, 257623, 257E23179, 257E2153

Abstract:

This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

Author:

Yu San Wang

ISBN #:

0275900460

Author:

Yu S. Wang

ISBN #:

0275934713

Author:

Yu Michael Wang

ISBN #:

0791835138