Yu Jia Wang

US Patent:

6934297, Aug 23, 2005

Filed:

Nov 2, 2000

Appl. No.:

09/704807

Inventors:

Brahim Bensaou - Kowloon, HK
Yu Wang - Santa Cruz CA, US

Assignee:

Agency for Science, Technology and Research - Singapore

International Classification:

H04L012/413

US Classification:

370445, 370348, 370443, 455450, 455451, 4554521

Abstract:

A communication unit () that wants to transmit a data packet to another communication unit () must acquire access to a common communication channel (not shown) before transmitting a data packet (). For data packets of realtime applications, quality of service (QOS) parameters for the data packet are used to define transmission parameters to communicate the data packet (). These parameters include T() and T(). In addition, compliance with predetermined requirements of size relationship between request-to-send (RTS) and clear-to-send (CTS) packets are imposed.

US Patent:

7492005, Feb 17, 2009

Filed:

Dec 28, 2005

Appl. No.:

11/321957

Inventors:

Hong Chang - Cupertino CA, US
Tiesheng Li - San Jose CA, US
Yu Wang - Fremont CA, US

Assignee:

Alpha & Omega Semiconductor, Ltd. - Hamilton

International Classification:

H01L 29/76

US Classification:

257330, 257340

Abstract:

This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric liner layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate. The MOSFET device has a reduced gate to drain capacitance Cgd depending on the controllable depth of the trenched gate disposed above the SGT structure formed as a round hole below the trenched gate.

US Patent:

7521332, Apr 21, 2009

Filed:

Mar 23, 2007

Appl. No.:

11/690581

Inventors:

Tiesheng Li - San Jose CA, US
Yu Wang - Fremont CA, US
Yingying Lou - Shanghai, CN
Anup Bhalla - Santa Clara CA, US

Assignee:

Alpha & Omega Semiconductor, Ltd - Hamilton

International Classification:

H01L 21/76

US Classification:

438426

Abstract:

A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut Dof the test structure is determined from the signal and an etch depth Dis determined from D. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.

US Patent:

7632733, Dec 15, 2009

Filed:

Apr 29, 2006

Appl. No.:

11/413248

Inventors:

Yu Wang - Fremont CA, US
Tiesheng Li - San Jose CA, US
Hong Chang - Cupertino CA, US

Assignee:

Alpha & Omega Semiconductor, Inc. - Sunnyvale CA

International Classification:

H01L 21/336

US Classification:

438270, 257E2153

Abstract:

This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

US Patent:

7633267, Dec 15, 2009

Filed:

Jul 5, 2005

Appl. No.:

11/175555

Inventors:

Keith Douglas Kepler - Belmont CA, US
Yu Wang - Foster City CA, US

Assignee:

Farasis Energy, Inc. - Hayward CA

International Classification:

H01M 10/46

US Classification:

320150

Abstract:

A high throughput combinatorial screening method and apparatus for the evaluation of electrochemical materials using a single voltage source () is disclosed wherein temperature changes arising from the application of an electrical load to a cell array () are used to evaluate the relative electrochemical efficiency of the materials comprising the array. The apparatus may include an array of electrochemical cells () that are connected to each other in parallel or in series, an electronic load () for applying a voltage or current to the electrochemical cells (), and a device (), external to the cells, for monitoring the relative temperature of each cell when the load is applied.

US Patent:

7710371, May 4, 2010

Filed:

Dec 16, 2004

Appl. No.:

11/014490

Inventors:

Ping Mei - Palo Alto CA, US
Jurgen Daniel - Mountain View CA, US
James B. Boyce - Los Altos CA, US
Jackson Ho - Palo Alto CA, US
Rachel Lau - San Jose CA, US
Yu Wang - Union City CA, US

Assignee:

Xerox Corporation - Norwalk CT

International Classification:

G09G 3/34
C25B 9/00
F04B 17/00
B41J 2/14
G02F 1/153
H04R 19/00

US Classification:

345 85, 204253, 204255, 204257, 204252, 4174131, 347 49, 359267, 359291, 381176, 381399

Abstract:

Cells can include variable volumes defined between a flexible structure, such as a polymer layer, and a support surface, with the flexible structure and support surface being attached in a first region that surrounds a second region in which they are unattached. Various adhesion structures can attach the flexible structure and the support surface. When unstretched, the flexible structure can lie in a flat position on the support surface. In response to a stretching force away from the support surface, the flexible structure can move out of the flat position, providing the variable volume. Electrodes, such as on the flexible structure, on the support surface, and over the flexible structure, can have charge levels that couple with each other and with the variable volume. A support structure can include a device layer with signal circuitry that provides a signal path between an electrode and external circuitry. One or more ducts can provide fluid communication with each cell's variable volume.

US Patent:

7795108, Sep 14, 2010

Filed:

Mar 6, 2009

Appl. No.:

12/399632

Inventors:

Tiesheng Li - San Jose CA, US
Yu Wang - Fremont CA, US
Yingying Lou - Shanghai CA, US
Anup Bhalla - Santa Clara CA, US

Assignee:

Alpha & Omega Semiconductor, Ltd - Hamilton

International Classification:

H01L 21/76

US Classification:

438426

Abstract:

A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut Dof the test structure is determined from the signal and an etch depth Dis determined from D. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.

US Patent:

7928507, Apr 19, 2011

Filed:

Dec 9, 2009

Appl. No.:

12/653130

Inventors:

Yu Wang - Fremont CA, US
Tiesheng Li - San Jose CA, US
Hong Chang - Cupertino CA, US

Assignee:

Alpha & Omega Semiconductor, Inc. - Sunnyvale CA

International Classification:

H01L 29/66
H01L 29/06

US Classification:

257330, 257622, 257E2153, 257E21585

Abstract:

This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

Author:

Yu San Wang

ISBN #:

0275900460

Author:

Yu S. Wang

ISBN #:

0275934713

Author:

Yu Michael Wang

ISBN #:

0791835138