Young J Park

US Patent:

6334229, Jan 1, 2002

Filed:

Jan 7, 1999

Appl. No.:

09/227272

Inventors:

Mansour Moinpour - Cupertino CA
Hoang T. Nguyen - San Jose CA
Mohsen Salek - Cupertino CA
Young C. Park - Mountain View CA
Tom Bramblett - Hillsboro OR
John M. deLarios - Palo Alto CA
Lynn S. Ryle - San Jose CA
Donald E. Anderson - Morgan Hill CA
Wilbur C. Krusell - San Jose CA

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

B01B 1102

US Classification:

15 77, 15 883, 15102, 451 44, 451245

Abstract:

An apparatus for cleaning edges of substrates is described. The present invention provides a cleaning mechanism that cleans particles off the edge of the wafer based on friction and/or a difference in tangential velocity at a point of contact between the wafer and the cleaning mechanism.

US Patent:

6357071, Mar 19, 2002

Filed:

Aug 3, 1998

Appl. No.:

09/128343

Inventors:

Monsour Moinpour - Cupertino CA
Ilan Berman - Sunnyvale CA
Young C. Park - Mountain View CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

B08B 700

US Classification:

15102, 15 77, 15 971, 15 882, 134902, 451 44, 451310

Abstract:

An apparatus for cleaning edges and/or bevel areas of substrates. In one embodiment, the present invention provides a cleaning mechanism that cleans particles off the edge of the wafer based upon friction at the contact point between the wafer and a rotating belt.

US Patent:

6475293, Nov 5, 2002

Filed:

Nov 16, 2000

Appl. No.:

09/715320

Inventors:

Monsour Moinpour - Cupertino CA
Ilan Berman - Sunnyvale CA
Young C. Park - Mountain View CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

B08B 700

US Classification:

134 6, 134902, 15 971, 15102, 451 44

Abstract:

An apparatus for cleaning edges and/or bevel areas of substrates. In one embodiment, the present invention provides a cleaning mechanism that cleans particles off the edge of the wafer based upon friction at the contact point between the wafer and a rotating belt.

US Patent:

6767439, Jul 27, 2004

Filed:

Nov 7, 2001

Appl. No.:

10/045849

Inventors:

Young Park - Palo Alto CA 94303

International Classification:

C23C 1434

US Classification:

20429825, 20429823, 20429835, 118719, 118729, 15634531, 15634554

Abstract:

The disclosure herein relates to a high throughput system for thin film deposition on substrates which can be used in applications such as optical disks, and in particular DVD disks, chip-scale packaging, and plastic based display, for example. An apparatus useful in the production of products of the kind described above includes: (a) a continuously moving web for simultaneously transporting a number of substrates to which a thin film of material is to be applied, wherein the moving web is a roll-to-roll moving web; (b) a central processing chamber which is maintained under vacuum and through which at least a portion of said continuously moving web travels; and, (c) at least one deposition device which is located within said central processing chamber, where at least a portion of said continuously moving web is exposed to material deposited from said deposition device. Typically the deposition device is a magnetron sputtering device. In addition, the apparatus typically also includes (d) a first moving platform which transfers a substrate onto said continuously moving web, and (e) a second moving platform which receives processed substrates from said continuously moving web.

US Patent:

7551909, Jun 23, 2009

Filed:

Aug 29, 2003

Appl. No.:

10/651500

Inventors:

Yongsam Moon - Cupertino CA, US
Young Soo Park - Sunnyvale CA, US
Deog-Kyoon Jeong - Kwanak-Gu, KR

Assignee:

Silicon Image, Inc. - Sunnyvale CA

International Classification:

H04B 1/06

US Classification:

455260, 455208, 455333, 375345, 331 19

Abstract:

A dual current path voltage controlled oscillator exhibits both the seamless frequency acquisition and uniform VCO gain reduction while preserving an original operating range and phase locked loop characteristics. The present invention provides a quad-channel transceiver comprising a phase locked loop circuit including a voltage controlled oscillator used to generate a clock signal, a FIFO buffer used to store data to be transmitted, a frequency comparator for comparing a reference clock to the generated clock signal from the phase locked loop circuit; and a folded starved inverter circuit contained within the voltage controlled oscillator wherein the folded starved inverter provides two current paths. The dual current paths allow for simultaneous coarse and fine phase tracking. With this low jitter performance and wide operating range, the quad transceiver may be implemented in 0.

US Patent:

8482686, Jul 9, 2013

Filed:

Feb 7, 2013

Appl. No.:

13/762276

Inventors:

Ming Xu - Sunnyvale CA, US
Young Bae Park - San Jose CA, US
Zhibing Ge - Sunnyvale CA, US
Daisuke Nozu - Kita, JP
Cheng Chen - San Jose CA, US
Abbas Jamshidi Roudbari - Sunnyvale CA, US
Shih Chang Chang - Cupertino CA, US
Shawn R. Gettemy - San Jose CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G02F 1/141
G02F 1/133
G09G 5/00

US Classification:

349 37, 349 33, 349 34, 345206, 345214

Abstract:

Display ground plane structures may contain slits. Image pixel electrodes in the display may be arranged in rows and columns. Image pixels in the display may be controlled using gate lines that are associated with the rows and data lines that are associated with the columns. An electric field may be produced by each image pixel electrode that extends through a liquid crystal layer to an associated portion of the ground plane. The slits in the ground plane may have a slit width. Data lines may be located sufficiently below the ground plane and sufficiently out of alignment with the slits to minimize crosstalk from parasitic electric fields. A three-column inversion scheme may be used when driving data line signals into the display, so that pairs of pixels that straddle the slits are each driven with a common polarity. Gate line scanning patterns may be used that enhance display uniformity.

US Patent:

20110298833, Dec 8, 2011

Filed:

Jun 4, 2010

Appl. No.:

12/794623

Inventors:

EnkhAmgalan Dorjgotov - Cupertino CA, US
Zhibing Ge - Sunnyvale CA, US
Ming Xu - Cupertino CA, US
Cheng Chen - Cupertino CA, US
Young Bae Park - San Jose CA, US
John Z. Zhong - Cupertino CA, US
Wei Chen - Palo Alto CA, US
Shawn Robert Gettemy - San Jose CA, US

Assignee:

APPLE INC. - Cupertino CA

International Classification:

G09G 3/36
G02F 1/1337
G09G 5/10
G02F 1/1335

US Classification:

345690, 349 96, 349123, 345 87

Abstract:

Devices and methods related to high-contrast liquid crystal displays (LCDs) are provided. For example, such an electronic device may include an LCD with two liquid crystal alignment layers not symmetric to one another and upper and lower polarizing layers respectively above and below the alignment layers. Light transmittance through the plurality of pixels may increase monotonically with gray scale voltage. The display may operate using a gray scale level voltage higher than a minimum gray scale level voltage capability of the display. Additionally or alternatively, liquid crystal molecular alignment axes of the two alignment layers may be offset from one another by an angle other than a multiple of 180 degrees. Additionally or alternatively, a first polarizing axis of the upper polarizing layer or a second polarizing axis of the lower polarizing layer, or both, may be neither parallel nor perpendicular to one of the liquid crystal molecular alignment axes.

US Patent:

20120327321, Dec 27, 2012

Filed:

Sep 23, 2011

Appl. No.:

13/243317

Inventors:

Chun-Yao Huang - Cupertino CA, US
Young Bae Park - San Jose CA, US
Shih Chang Chang - Cupertino CA, US

Assignee:

APPL INC. - Cupertino CA

International Classification:

G02F 1/136
H01L 21/336

US Classification:

349 42, 438151, 257E21409

Abstract:

Disclosed embodiments relate to a thin-film transistor (TFT) for use in a display device. The display device may include a liquid crystal display (LCD) panel having multiple pixels arranged in rows and column, with each row corresponding to a gate line and each column corresponding to a source line. Each of the pixels includes a pixel electrode and a TFT. The TFT may include a metal oxide semiconductor channel between a source and drain. For each TFT, holes may be formed in the gate line in a region beneath the source and/or the drain. The holes may be formed such that the source and drain only partially overlap the holes. The presence of the holes reduces the area of the gate line, which may reduce parasitic capacitance and improve loading. This may provide improved panel performance, which may reduce the appearance of certain visual artifacts.