Yongchul C Ahn

US Patent:

6770566, Aug 3, 2004

Filed:

May 16, 2002

Appl. No.:

10/151127

Inventors:

Yongchul Ahn - Eagan MN
Kaichiu Wong - Sunnyvale CA

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H01L 21302

US Classification:

438710, 438 70

Abstract:

A method of forming a semiconductor structure is described that includes etching a first metal layer at the bottom of a via in a first insulating layer to expose a second metal layer, wherein the first metal layer is on the second metal layer, and wherein the etching of the first metal layer is not reactive-ion etching. Methods of making semiconductor devices and electronic devices are also described.

US Patent:

7965538, Jun 21, 2011

Filed:

Jul 13, 2009

Appl. No.:

12/502224

Inventors:

Yongchul Ahn - Eagan MN, US
Antoine Khoueir - Apple Valley MN, US
Shuiyuan Huang - Apple Valley MN, US
Peter Nicholas Manos - Eden Prairie MN, US
Maroun Khoury - Burnsville MN, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G11C 11/00

US Classification:

365148, 365171, 365226

Abstract:

Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal. A formation current is applied through the RRAM cell, and an activation voltage is concurrently applied to the APD to maintain a maximum magnitude of the formation current below a predetermined threshold level.

US Patent:

7998758, Aug 16, 2011

Filed:

Feb 20, 2009

Appl. No.:

12/389422

Inventors:

Yongchul Ahn - Eagan MN, US
Shuiyuan Haung - Apple Valley MN, US
Antoine Khoueir - Apple Valley MN, US
Paul Anderson - Eden Prairie MN, US
Lili Jia - Edina MN, US
Christina Laura Hutchinson - Eden Prairie MN, US
Ivan Ivanov - Apple Valley MN, US
Dimitar Dimitrov - Edina MN, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

H01L 29/04
H01L 29/82

US Classification:

438 3, 257421, 257E29323

Abstract:

A magnetic element and a method for making a magnetic element. The method includes patterning a first electrode material to form a first electrode on a substrate and depositing filler material on the substrate around the first electrode. The method further includes polishing to form a planar surface of filler and the first electrode. A magnetic cell is formed on the planar surface and a second electrode is formed on the magnetic cell. In some embodiments, the first electrode has an area that is at least 2:1 to the area of the magnetic cell.

US Patent:

8030172, Oct 4, 2011

Filed:

May 12, 2003

Appl. No.:

10/436411

Inventors:

Yongchul Ahn - Eagan MN, US
Kaichiu Wong - Sunnyvale CA, US
Venuka Jayatilaka - Savage MN, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H01L 21/76

US Classification:

438435, 257E21546

Abstract:

A semiconductor structure has a substrate having a trench, an isolation dielectric in the trench, and a stress buffer layer, between the substrate and the dielectric. Semiconductor devices containing the semiconductor structure may have higher reliability, and may have a reduced manufacturing costs per device.

US Patent:

8183126, May 22, 2012

Filed:

Jul 13, 2009

Appl. No.:

12/502178

Inventors:

Hyung-Kyu Lee - Edina MN, US
YoungPil Kim - Eden Prairie MN, US
Peter Nicholas Manos - Eden Prairie MN, US
Maroun Khoury - Burnsville MN, US
Dadi Setiadi - Edina MN, US
Chulmin Jung - Eden Prairie MN, US
Hsing-Kuen Liou - Plymouth MN, US
Yongchul Ahn - Eagan MN, US
Jinyoung Kim - Edina MN, US
Antoine Khoueir - Apple Valley MN, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

H01L 21/30

US Classification:

438455, 257379, 257E27081

Abstract:

Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.

US Patent:

8194438, Jun 5, 2012

Filed:

Feb 12, 2009

Appl. No.:

12/370164

Inventors:

Yongchul Ahn - Eagan MN, US
Antoine Khoueir - Apple Valley MN, US
Yong Lu - Rosemount MN, US
Hongyue Liu - Maple Grove MN, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G11C 11/00

US Classification:

365158, 365154, 36518508, 365171

Abstract:

Non-volatile static random access memory (nvSRAM) that has a six transistor static random access memory (6T SRAM) cell electrically connected to a non-volatile random access memory (nvRAM) cell. The nvRAM cell has first and second variable magnetic resistors and first, second and third transistors.

US Patent:

8227783, Jul 24, 2012

Filed:

Jul 13, 2009

Appl. No.:

12/501533

Inventors:

Andreas Roelofs - Eden Prairie MN, US
Markus Siegert - Minneapolis MN, US
Venugopalan Vaithyanathan - Bloomington MN, US
Wei Tian - Bloomington MN, US
Yongchul Ahn - Eagan MN, US
Muralikrishnan Balakrishnan - Eden Prairie MN, US
Olle Heinonen - Eden Prairie MN, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

H01L 29/02

US Classification:

257 2, 438104

Abstract:

A resistive sense memory cell includes a layer of crystalline praseodymium calcium manganese oxide and a layer of amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack. A first and second electrode are separated by the resistive sense memory stack. The resistive sense memory cell can further include an oxygen diffusion barrier layer separating the layer of crystalline praseodymium calcium manganese oxide from the layer of amorphous praseodymium calcium manganese oxide a layer. Methods include depositing an amorphous praseodymium calcium manganese oxide disposed on the layer of crystalline praseodymium calcium manganese oxide forming a resistive sense memory stack.

US Patent:

8615868, Dec 31, 2013

Filed:

Nov 29, 2011

Appl. No.:

13/306887

Inventors:

Yongchul Ahn - San Jose CA, US
Xiaozhong Dang - Fremont CA, US
Quang Le - San Jose CA, US
Simon H. Liao - Fremont CA, US

Assignee:

HGST Netherlands B.V. - Amsterdam

International Classification:

G11B 5/127
H04R 31/00

US Classification:

2960316, 2960312, 2960313, 2960314, 2960315, 2960318, 216 62, 216 65, 216 66, 3603241, 36032411, 36032412, 3603242, 451 5, 451 41

Abstract:

A method for manufacturing a magnetic sensor that includes depositing a plurality of mask layers, then forming a stripe height defining mask over the sensor layers. A first ion milling is performed just sufficiently to remove portions of the free layer that are not protected by the stripe height defining mask, the first ion milling being terminated at the non-magnetic barrier or spacer layer. A dielectric layer is then deposited, preferably by ion beam deposition. A second ion milling is then performed to remove portions of the pinned layer structure that are not protected by the mask, the free layer being protected during the second ion milling by the dielectric layer.