Yaoling Pan

US Patent:

7795125, Sep 14, 2010

Filed:

Nov 20, 2008

Appl. No.:

12/274904

Inventors:

Mihai A. Buretea - San Francisco CA, US
Jian Chen - Mountain View CA, US
Calvin Y. H. Chow - Portola Valley CA, US
Chunming Niu - Palo Alto CA, US
Yaoling Pan - East Windsor NJ, US
J. Wallace Parce - Palo Alto CA, US
Linda T. Romano - Sunnyvale CA, US
David P. Stumbo - Belmont CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

H01L 21/28
H01L 21/3205

US Classification:

438602, 438197, 438603, 257E214, 257E2105, 257E2117, 257E21464

Abstract:

The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally includes separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into a electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.

US Patent:

7871870, Jan 18, 2011

Filed:

Feb 9, 2010

Appl. No.:

12/703043

Inventors:

Shahriar Mostarshed - San Mateo CA, US
Jian Chen - Sunnyvale CA, US
Francisco A. Leon - Palo Alto CA, US
Yaoling Pan - East Windsor NJ, US
Linda T. Romano - Sunnyvale CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

H01L 21/00
H01L 27/108

US Classification:

438151, 438585, 257296, 257368, 257E51006

Abstract:

Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

US Patent:

20080128688, Jun 5, 2008

Filed:

Jan 18, 2008

Appl. No.:

12/016701

Inventors:

Yaoling Pan - East Windsor NJ, US
Francisco Leon - Palo Alto CA, US
David P. Stumbo - Belmont CA, US

Assignee:

NANOSYS, INC. - Palo Alto CA

International Classification:

H01L 51/05

US Classification:

257 40, 257E51005

Abstract:

The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

US Patent:

20100167512, Jul 1, 2010

Filed:

Mar 9, 2010

Appl. No.:

12/720125

Inventors:

Yaoling Pan - East Windsor NJ, US
Jian Chen - Sunnyvale CA, US
Francisco Leon - Palo Alto CA, US
Shahriar Mostarshed - San Mateo CA, US
Linda T. Romano - Sunnyvale CA, US
Vijendra Sahi - Menlo Park CA, US
David P. Stumbo - Belmont CA, US

Assignee:

NANOSYS, INC. - Palo Alto CA

International Classification:

H01L 21/22

US Classification:

438549, 257E21135, 977762

Abstract:

Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure.

US Patent:

20100323500, Dec 23, 2010

Filed:

Aug 11, 2010

Appl. No.:

12/854323

Inventors:

Mihai Buretea - San Francisco CA, US
Jian Chen - Sunnyvale CA, US
Calvin Chow - Portola Valley CA, US
Chunming Niu - Palo Alto CA, US
Yaoling Pan - East Windsor NJ, US
J. Wallace Parce - Palo Alto CA, US
Linda T. Romano - Sunnyvale CA, US
David Stumbo - Belmont CA, US

Assignee:

NANOSYS, INC. - Palo Alto CA

International Classification:

H01L 21/20

US Classification:

438478, 257E2109

Abstract:

The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally includes separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into a electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.

US Patent:

20120242627, Sep 27, 2012

Filed:

Mar 21, 2011

Appl. No.:

13/052446

Inventors:

Cheonhong Kim - San Diego CA, US
John Hyunchul Hong - San Diego CA, US
Yaoling Pan - San Diego CA, US

Assignee:

QUALCOMM MEMS TECHNOLOGIES - San Diego CA

International Classification:

G06F 3/038
H01L 29/24
H01L 29/04
H01L 21/385

US Classification:

345204, 438104, 257 43, 257 61, 257E21468, 257E29101, 257E29003

Abstract:

This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source region, a drain region, and a channel region between the source region and the drain region is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel region, and a first metal layer on the dielectric layer. A second metal layer is formed on the oxide semiconductor layer overlying the source region and the drain region. The oxide semiconductor layer and the second metal layer are treated to form a heavily doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source region and the drain region. An oxide in the second metal layer also can be formed.

US Patent:

20130037793, Feb 14, 2013

Filed:

Aug 11, 2011

Appl. No.:

13/208250

Inventors:

Yaoling PAN - San Diego CA, US
Cheonhong KIM - San Diego CA, US
Tallis Young CHANG - San Diego CA, US

Assignee:

QUALCOMM MEMS TECHNOLOGIES, INC. - San Diego CA

International Classification:

H01L 29/786
H01L 33/08
H01L 21/36

US Classification:

257 43, 438104, 438285, 257 59, 257E21461, 257E29296, 257E33053

Abstract:

This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source area, a drain area, and a channel area is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel area of the substrate, and a first metal layer on the dielectric layer. Hydrogen ions are implanted with a plasma-immersion ion implantation process in the oxide semiconductor layer overlying the source area and the drain area of the substrate. The hydrogen ion implantation forms a doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source area and the drain area of the substrate.

US Patent:

20130100143, Apr 25, 2013

Filed:

Oct 20, 2011

Appl. No.:

13/278080

Inventors:

Yaoling PAN - San Diego CA, US
Lixia ZHOU - Milpitas CA, US

Assignee:

QUALCOMM MEMS TECHNOLOGIES, INC. - San Diego CA

International Classification:

G06T 1/00
G02B 26/00

US Classification:

345501, 359290

Abstract:

This disclosure provides systems, methods and apparatus for a via structure. In one aspect, an apparatus includes a substrate and a first electromechanical systems device on a surface of the substrate. The first electromechanical systems device includes a first metal layer and a second metal layer. A first via structure can be included on the surface of the substrate. The first via structure includes the first metal layer, the second metal layer, and a third metal layer. The first metal layer of the first electromechanical systems device may be the same metal layer as the first metal layer of the first via structure.