Yaoling Ling Pan

US Patent:

6678435, Jan 13, 2004

Filed:

May 18, 2001

Appl. No.:

09/861120

Inventors:

Yaoling Pan - Sunnyvale CA
Michele Palmieri - Agrate Brianza, IT
Richard E. Haven - Sunnyvale CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA
ST Microelectronics, Inc. - Carrollton TX

International Classification:

G02B 626

US Classification:

385 16

Abstract:

An optical switch having an insulator under a heater element is disclosed. The insulator reduces the heat loss thereby making the switch more efficient. The insulator is fabricated embedded in the underlying substrate on which the heater and the optical intersection are fabricated. A method of fabricating the optical switch having an insulator is disclosed. A trench is etched on the substrate and filled with oxide or other suitable insulating material. Then, the heater and the optical intersection are fabricated above the insulator.

US Patent:

7105428, Sep 12, 2006

Filed:

Apr 29, 2005

Appl. No.:

11/117703

Inventors:

Yaoling Pan - Union City CA, US
Xiangfeng Duan - Mountain View CA, US
Robert S. Dubrow - San Carlos CA, US
Jay L. Goldman - Mountain View CA, US
Shahriar Mostarshed - San Mateo CA, US
Chunming Niu - Palo Alto CA, US
Linda T. Romano - Sunnyvale CA, US
Dave Stumbo - Belmont CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

H01L 21/20
H01L 21/477
H01L 21/31
H01L 23/48
H01L 29/40
B01J 27/22
H01L 21/44

US Classification:

438584, 438795, 438798, 438962, 438759, 257734, 257746, 257E5104, 977742, 977843, 977743

Abstract:

The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

US Patent:

7115971, Oct 3, 2006

Filed:

Mar 23, 2004

Appl. No.:

10/806361

Inventors:

David Stumbo - Belmont CA, US
Jian Chen - Mountain View CA, US
David Heald - Solvang CA, US
Yaoling Pan - Union City CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

H01L 29/93

US Classification:

257600, 257E2907, 977762, 438379

Abstract:

A nanowire varactor diode and methods of making the same are disclosed. The structure comprises a coaxial capacitor running the length of the semiconductor nanowire. In one embodiment, a semiconductor nanowire of a first conductivity type is deposited on a substrate. An insulator is formed on at least a portion of the nanowire's surface. A region of the nanowire is doped with a second conductivity type material. A first electrical contact is formed on at least part of the insulator and the doped region. A second electrical contact is formed on a non-doped potion of the nanowire. During operation, the conductivity type at the surface of the nanowire inverts and a depletion region is formed upon application of a voltage to the first and second electrical contacts. The varactor diode thereby exhibits variable capacitance as a function of the applied voltage.

US Patent:

7273732, Sep 25, 2007

Filed:

Jul 21, 2006

Appl. No.:

11/490636

Inventors:

Yaoling Pan - Union City CA, US
Xiangfeng Duan - Mountain View CA, US
Robert S. Dubrow - San Carlos CA, US
Jay L. Goldman - Mountain View CA, US
Shahriar Mostarshed - San Mateo CA, US
Chunming Niu - Palo Alto CA, US
Linda T. Romano - Sunnyvale CA, US
Dave Stumbo - Belmont CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

H01L 51/40

US Classification:

435 99, 438510, 438514, 438689, 257E51038, 257E5104, 977742

Abstract:

The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

US Patent:

7339184, Mar 4, 2008

Filed:

Apr 29, 2005

Appl. No.:

11/117707

Inventors:

Linda T. Romano - Sunnyvale CA, US
Jian Chen - Mountain View CA, US
Xiangfeng Duan - Mountain View CA, US
Robert S. Dubrow - San Carlos CA, US
Stephen A. Empedocles - Menlo Park CA, US
Jay L. Goldman - Mountain View CA, US
James M. Hamilton - Sunnyvale CA, US
David L. Heald - Solvang CA, US
Francesco Lemmi - Sunnyvale CA, US
Chunming Niu - Palo Alto CA, US
Yaoling Pan - Union City CA, US
George Pontis - Redwood City CA, US
Vijendra Sahi - Menlo park CA, US
Erik C. Scher - San Francisco CA, US
David P. Stumbo - Belmont CA, US
Jeffery A. Whiteford - Belmont CA, US

Assignee:

Nanosys, Inc - Palo Alto CA

International Classification:

H01L 29/00

US Classification:

257 1, 117 84, 257E21001, 977938

Abstract:

The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into electronic devices that include placing an outer surface of a cylinder in contact with a fluid suspension of nanowires and rolling the nanowire coated cylinder to deposit nanowires onto a surface. Methods are also provided to deposit nanowires using an ink-jet printer or an aperture to align nanowires. Additional aspects of the invention provide methods for preventing gate shorts in nanowire based transistors. Additional methods for harvesting and integrating nanowires are provided.

US Patent:

7345307, Mar 18, 2008

Filed:

Sep 22, 2005

Appl. No.:

11/233503

Inventors:

Yaoling Pan - Union City CA, US
Francisco Leon - Palo Alto CA, US
David P. Stumbo - Belmont CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

H01L 29/10

US Classification:

257 57, 257 40, 257 72, 257347, 257E21007, 977762, 977763, 977764

Abstract:

The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

US Patent:

7473943, Jan 6, 2009

Filed:

Sep 22, 2005

Appl. No.:

11/233398

Inventors:

Shahriar Mostarshed - San Mateo CA, US
Jian Chen - Mountain View CA, US
Francisco Leon - Palo Alto CA, US
Yaoling Pan - Union City CA, US
Linda T. Romano - Sunnyvale CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

H01L 29/80

US Classification:

257213, 257296, 257368, 257784, 257E51006, 977762, 977932, 977938

Abstract:

Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

US Patent:

7569503, Aug 4, 2009

Filed:

Nov 10, 2005

Appl. No.:

11/271488

Inventors:

Yaoling Pan - Union City CA, US
David P. Stumbo - Belmont CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

H01L 21/00

US Classification:

438795, 438799, 257E21471, 257E21475, 977901, 977963

Abstract:

Embodiments of the present invention are provided for improved contact doping and annealing systems and processes. In embodiments, a plasma ion immersion implantation (PIII) process is used for contact doping of nanowires and other nanoelement based thin film devices. According to further embodiments of the present invention, pulsed laser annealing using laser energy at relatively low laser fluences below about 100 mJ/cm(e. g. , less than about 50 mJ/cm, e. g. , between about 2 and 18 mJ/cm) is used to anneal nanowire and other nanoelement-based devices on substrates, such as low temperature flexible substrates, e. g. , plastic substrates.