Xiaoying Shen

US Patent:

20170132344, May 11, 2017

Filed:

Oct 12, 2016

Appl. No.:

15/291459

Inventors:

- REDWOOD CITY CA, US
Xiaoying Shen - Austin TX, US
Sebastian Turullols - Los Altos CA, US

International Classification:

G06F 17/50
G06F 17/16
G06F 17/11

Abstract:

Embodiments include systems and methods for optimization of micro-benchmark analysis for microprocessor designs. For example, embodiments seek to generate a suite of micro-benchmarks and associated weighting factors, which can be used to effectively define a weighted aggregate workload condition for a fine-grained (e.g., RTL) simulation in a manner that is a sufficient proxy for predicted commercial workload conditions. The suite of micro-benchmarks can be appreciably more efficient to simulate than the commercial workload, so that using the suite of micro-benchmarks as a proxy for the commercial workload can provide many benefits, including more efficient iterative design.

US Patent:

20160048187, Feb 18, 2016

Filed:

Aug 15, 2014

Appl. No.:

14/461042

Inventors:

- Redwood City CA, US
Xiaoying Shen - Austin TX, US
Sebastian Turullols - Los Altos CA, US
Robert T. Golla - Round Rock TX, US

International Classification:

G06F 1/32

Abstract:

Embodiments of the invention provide adaptive power ramp control (APRC) in microprocessors. One implementation of the APRC can compute a present core power and a present power ramp condition in the microprocessor, for example, to determine whether the present power is in a particular predefined control zone and whether the present power ramp is greater than a predefined threshold for that control zone. Those determinations can indicate a likelihood of an imminent, undesirable power ramp condition and can inform entry into a control mode. The APRC can generate an appropriate stall control signal in response to its present control mode, and the stall control signal can stall operation of at least one functional unit of the microprocessor according to a predefined stall pattern. This can effectively combat the imminent power ramp condition by reducing the power usage of the microprocessor.

US Patent:

20150347666, Dec 3, 2015

Filed:

Jun 2, 2014

Appl. No.:

14/293763

Inventors:

- Redwood City CA, US
Xiaoying Shen - Austin TX, US
Sebastian Turullols - Los Altos CA, US

International Classification:

G06F 17/50

Abstract:

Embodiments include systems and methods for optimization of micro-benchmark analysis for microprocessor designs. For example, embodiments seek to generate a suite of micro-benchmarks and associated weighting factors, which can be used to effectively define a weighted aggregate workload condition for a fine-grained (e.g., RTL) simulation in a manner that is a sufficient proxy for predicted commercial workload conditions. The suite of micro-benchmarks can be appreciably more efficient to simulate than the commercial workload, so that using the suite of micro-benchmarks as a proxy for the commercial workload can provide many benefits, including more efficient iterative design.

US Patent:

20150301832, Oct 22, 2015

Filed:

Apr 18, 2014

Appl. No.:

14/256347

Inventors:

- Redwood City CA, US
Xiaoying Shen - Austin TX, US
Manish Shah - Austin TX, US

International Classification:

G06F 9/38
G06F 9/30

Abstract:

Embodiments for a processor that selectively enables and disables branch prediction are disclosed. The processor may include counters to track a number of fetched instructions, a number of branches, and a number of mispredicted branches. A misprediction threshold may be calculated dependent upon the tracked number of branches and a predefined misprediction ratio. Branch prediction may then be disabled when the number of mispredictions exceed the determined threshold value and dependent upon the branch rate.