Sharon X Shi

age ~64

from San Jose, CA

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Also known as:

Xiaorong Sharon Shi
Xiaorong S Shi
Xiao Rong Shi
Sharon Shi Xiaorong
Xiaorong S Xu
Xiao-Rong Shi
Shi Xiaorong
Xiadrong Shi

Connected to:

Sharon Shi Phones & Addresses

San Jose, CA
Chicago, IL
Skokie, IL
Fremont, CA
Santa Clara, CA
Middle Island, NY
Batavia, IL

Work

Company:

BlueGreen Realty, Inc
Address:

8254 Kimball Avenue, Skokie, IL 60076
Phones:

646 404-4472

Images

Specialities

Buyer's Agent • Listing Agent • Relocation

Real Estate Brokers

Sharon Shi, Chicago IL Broker

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Specialties:

Residential sales
Luxury homes
First time home buyers
Relocation
Property Management

Work:

BlueGreen Realty
Chicago, IL
646 404-4472 (Phone)
License #475.154397

Client type:

Home Buyers
Home Sellers

Property type:

Single Family Home
Condo/Townhome
Multi-family

Sharon Shi, Skokie IL

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Specialties:

Buyer's Agent
Listing Agent
Relocation

Work:

BlueGreen Realty, Inc
8254 Kimball Avenue, Skokie, IL 60076
646 404-4472 (Office)

Links:

Site
Facebook
LinkedIn

Us Patents

Super Trench Mosfet Including Buried Source Electrode
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US Patent:

7557409, Jul 7, 2009
Filed:

Jan 26, 2007
Appl. No.:

11/698519
Inventors:

Deva N. Pattanayak - Saratoga CA, US
Yuming Bai - Union City CA, US
Kyle Terrill - Santa Clara CA, US
Christiana Yue - Milpitas CA, US
Robert Xu - Fremont CA, US
Kam Hong Lui - Santa Clara CA, US
Kuo-In Chen - Los Altos CA, US
Sharon Shi - San Jose CA, US
Assignee:

Siliconix Incorporated - Santa Clara CA
International Classification:

H01L 29/76
US Classification:

257333, 257E29027, 257E29262
Abstract:

In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Method Of Fabricating Super Trench Mosfet Including Buried Source Electrode
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US Patent:

7704836, Apr 27, 2010
Filed:

Mar 31, 2008
Appl. No.:

12/080031
Inventors:

Deva N. Pattanayak - Saratoga CA, US
Yuming Bai - Union City CA, US
Kyle Terrill - Santa Clara CA, US
Christiana Yue - Milpitas CA, US
Robert Xu - Fremont CA, US
Kam Hong Lui - Santa Clara CA, US
Kuo-In Chen - Los Altos CA, US
Sharon Shi - San Jose CA, US
Assignee:

Siliconix incorporated - Santa Clara CA
International Classification:

H01L 21/336
US Classification:

438268, 438242, 438248, 438259, 438391, 438700, 257135, 257136, 257242, 257329, 257E27091, 257E27095, 257E29118, 257E29313, 257E21629, 257E21643
Abstract:

In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Trench Metal Oxide Semiconductor With Recessed Trench Material And Remote Contacts
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US Patent:

8368126, Feb 5, 2013
Filed:

Apr 7, 2008
Appl. No.:

12/098950
Inventors:

Deva N. Pattanayak - Saratoga CA, US
Kyle Terrill - Santa Clara CA, US
Sharon Shi - San Jose CA, US
Misha Lee - San Jose CA, US
Yuming Bai - Union City CA, US
Kam Lui - Santa Clara CA, US
Kuo-In Chen - Los Altos CA, US
Assignee:

Vishay-Siliconix - Santa Clara CA
International Classification:

H01L 29/80
US Classification:

257260, 257280, 257284, 257330, 257E29201
Abstract:

Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.

Ultra-Low Drain-Source Resistance Power Mosfet
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US Patent:

8409954, Apr 2, 2013
Filed:

Mar 21, 2006
Appl. No.:

11/386927
Inventors:

Sharon Shi - San Jose CA, US
Qufei Chen - San Jose CA, US
Martin Hernandez - San Jose CA, US
Deva Pattanayak - Saratoga CA, US
Kyle Terrill - Santa Clara CA, US
Kuo-In Chen - Los Altos CA, US
Assignee:

Vishay-Silconix - Santa Clara CA
International Classification:

H01L 21/336
US Classification:

438270, 257341, 257E29257, 257E2926
Abstract:

Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorous. The novel red Phosphorous doped substrate enables a desirable low drain-source resistance.

Super Trench Mosfet Including Buried Source Electrode And Method Of Fabricating The Same
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US Patent:

20050242392, Nov 3, 2005
Filed:

Apr 30, 2004
Appl. No.:

10/836833
Inventors:

Deva Pattanayak - Saratoga CA, US
Yuming Bai - Union City CA, US
Kyle Terrill - Santa Clara CA, US
Christiana Yue - Milpitas CA, US
Robert Xu - Fremont CA, US
Kam Lui - Santa Clara CA, US
Kuo-In Chen - Los Altos CA, US
Sharon Shi - San Jose CA, US
Assignee:

Siliconix incorporated - Santa Clara CA
International Classification:

H01L029/94
H01L021/8238
US Classification:

257328000, 438212000, 257330000, 438589000
Abstract:

In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Ultra-Low Drain-Source Resistance Power Mosfet
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US Patent:

20080157281, Jul 3, 2008
Filed:

Feb 11, 2008
Appl. No.:

12/069712
Inventors:

Sharon Shi - San Jose CA, US
Qufei Chen - San Jose CA, US
Martin Hernandez - San Jose CA, US
Deva Pattanayak - Saratoga CA, US
Kyle Terrill - Santa Clara CA, US
Kuo-In Chen - Los Altos CA, US
International Classification:

H01L 29/36
US Classification:

257607, 257E29109, 257E29024
Abstract:

Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorus. The novel red Phosphorus doped substrate enables a desirable low drain-source resistance.

Mosfet Active Area And Edge Termination Area Charge Balance
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US Patent:

20090090967, Apr 9, 2009
Filed:

Sep 3, 2008
Appl. No.:

12/203846
Inventors:

Qufei Chen - San Jose CA, US
Kyle Terrill - Santa Clara CA, US
Sharon Shi - San Jose CA, US
Assignee:

VISHAY-SILICONIX - Santa Clara CA
International Classification:

H01L 29/78
H01L 21/265
H01L 21/336
US Classification:

257330, 438524, 438270, 257E21334, 257E2141, 257E29262
Abstract:

A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson.

Method Of Fabricating Super Trench Mosfet Including Buried Source Electrode
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US Patent:

20100019316, Jan 28, 2010
Filed:

Sep 29, 2009
Appl. No.:

12/586906
Inventors:

Deva N. Pattanayak - Saratoga CA, US
Yuming Bai - Union City CA, US
Kyle Terrill - Santa Clara CA, US
Christiana Yue - Milpitas CA, US
Robert Xu - Fremont CA, US
Kam Hong Lui - Santa Clara CA, US
Kuo-In Chen - Los Altos CA, US
Sharon Shi - San Jose CA, US
Assignee:

Siliconix incorporated - Santa Clara CA
International Classification:

H01L 29/78
US Classification:

257330, 257E29262
Abstract:

A method of fabricating a trench MOSFET, the lower portion of the trench containing a buried source electrode which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Name / Title

Company / Classification

Phones & Addresses

Sharon Shi
Executive Director

21ST Century Institute
Business Associations

1000 Jorie Blvd STE 21, Oak Brook, IL 60523
630 574-2175, 630 574-2121

Resumes

Innovations Associate At Smgx

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Location:

Greater Chicago Area

Industry:

Marketing and Advertising

Engineering Manager

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Location:

San Jose, CA

Industry:

Electrical/Electronic Manufacturing

Work:

Vishay Intertechnology, Inc.
Engineering Manager
Vishay Siliconix
Process Integration Manager
Vishay Siliconix May 1997 - 2006
Staff Process Engineer

Skills:

Semiconductors
Semiconductor Industry
Failure Analysis
Mixed Signal
Silicon
Electronics
Analog
Process Integration
Product Engineering

Operations Manager

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Location:

Aurora, IL

Industry:

Printing

Work:

Diamond Envelope
Operations Manager

Managing Attorney

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Location:

Mchenry, IL

Industry:

Law Practice

Work:

Adf Jul 2010 - Feb 2011
Eb5 Attorney
Law Offices of Sharon Shi Jul 2010 - Feb 2011
Managing Attorney
Legal Immigrant Association Mar 2008 - Dec 2010
Board Member and Immigration Counselor
Choi & Wagreich Jan 2008 - Feb 2010
Associate Attorney

Education:

Chicago - Kent College of Law, Illinois Institute of Technology 2003 - 2004
East China University of Political Science and Law 2001 - 2004
Masters, Law Chicago - Kent College of Law
Chicago - Kent College of Law, Illinois Institute of Technology
Doctor of Jurisprudence, Doctorates

Skills:

Immigration Issues
Management Consulting
Management
Marketing
Mandarin
Public Speaking
Immigration Law
Entrepreneurship
Adjustment of Status
Joint Ventures
Business Development
Legal Writing
International Business
Research
Foreign Investment
Marketing Strategy
Commercial Litigation
Corporate Finance
Corporate Governance
Legal Advice
Appeals
International Relations
Legal Assistance
Mediation
Intellectual Property
Legal Issues
Valuation
Labor Certification
Arbitration
Financial Analysis
Courts
Civil Litigation
Employment Law
Licensing
E 2
Chinese
Market Research
English
International Trade
Administrative Law
Social Media
Financial Modeling
Bankruptcy
Time Management
L 1
Portfolio Management
Analysis
Emerging Markets
Event Management
Market Analysis

Senior Accountant And Operations Manager

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Work:

Baird & Warner Jun 2001 - Nov 2004
Accounting Manager
Diamond Envelope Jun 2001 - Nov 2004
Senior Accountant and Operations Manager
Monett Metals Aug 1996 - Jun 2001
Controller
Southern Illinois University May 1993 - Aug 1996
Research Assistant

Education:

Southern Illinois University, Carbondale 1993 - 1996
Masters, Accountancy Peking University
Masters, Master of Arts Peking University
Bachelors, Bachelor of Arts

Sharon Shi

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Eb-5 Attorney And China Project Liaison

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Position:

Managing Director at Law Offices of Sharon Shi, Immigration Attorney at Law Offices of Sharon Shi, Board Member at InternshipDesk

Location:

Greater Chicago Area

Industry:

Law Practice

Work:

Law Offices of Sharon Shi since Jun 2011
Managing Director
Law Offices of Sharon Shi since Jan 2011
Immigration Attorney
InternshipDesk - Chicago, IL since Jan 2011
Board Member

Education:

Chicago-Kent College of Law, Illinois Institute of Technology 2003 - 2004
Master of Law, International Intellectual Property Law East China University of Politics and Law 2001 - 2004
Master of Law, Criminal Law

Skills:

Immigration Law
Entrepreneurship
Mandarin
Management Consulting
Business Development
Immigration Issues

Interests:

Karaoke, traveling, food

Honor & Awards:

BEST OWNER - RATED BY MY DOG. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ PLEASE VOTE FOR LIA 1. Immigration Daily (www.ilw.com) Gave Credit to LIA for 485 Inventory Data disclosure:http://www.ilw.com/immigdaily/digest/2009,0928.shtm#comment 2. From April to early September 2008, LIA members visited offices of 30 legislators nationwide, and submitted LIA’s petitions for legal immigration reform. Emphasis was on members of the Sub-committee on Immigration and the Judiciary Committee of the House of Representatives. Following these visits, Congressmen Michael Honda, Sheila Jackson-Lee and Mel Watt became co-sponsors of Congresswoman Lofgren’s Visa Recapture bill (H.R. 5882). Congressman David Wu will co-sponsor both the Visa Recapture bill and STEM bill (H.R. 6039) of Congresswoman Lofgren. 3. Initiated lobbying to introduce a bill which was later introduced by Senator Gillibrand to increase Chinese employment visa quota (Accept Chinese Talent Now Act of 2009 - S.1182）.