Xiaojie He

US Patent:

6348813, Feb 19, 2002

Filed:

Nov 22, 2000

Appl. No.:

09/721153

Inventors:

Om P. Agrawal - Los Altos CA
Claudia A. Stanley - Austin TX
Xiaojie (Warren) He - Austin TX
Larry R. Metzger - Austin TX
Robert A. Simon - Colorado Springs CO
Kerry A. Ilgenstein - Austin TX

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19177

US Classification:

326 41, 326 40, 326 39, 326 38

Abstract:

An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSMs). An even number of Super Logic Blocks (SLBs) are coupled to each SSM. Each SSM and its SLBs define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PTs) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications.

US Patent:

6653860, Nov 25, 2003

Filed:

Aug 10, 2001

Appl. No.:

09/927793

Inventors:

Om P. Agrawal - Los Altos CA
Xiaojie (Warren) He - Austin TX
Claudia A. Stanley - Austin TX
Larry R. Metzger - Austin TX
Chong M. Lee - Colorado Springs CO

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19177

US Classification:

326 41, 326 38

Abstract:

An improved, high density CPLD includes a plurality of macrocell sections. Each macrocell section can receive a relatively large number of independent input terms and can generate as a base cluster, at least as many as 5 different product term signals (PTs) therefrom. Part or all of the macrocells local 5 PTs may be used for generating a local sum-of-products (SoP) signal in a local, first-level ORring operation. Additionally SoPs generated in neighboring macrocell sections may be selectively and incrementally cascaded (cross-laced) for supplemental summing into the local SoP signal. SoP signals of neighboring sections may be further selected in a sums sharing array for second level summing. The combination of the first-level cascading (cross-lacing) and second-level sums sharing provides a wide range of programmably selectable granulations including that of having relatively fast generation of a sum of just a few PTs (e. g. , 5 PTs) to having slower generation of sums of a much larger number of PTs (e. g.

US Patent:

7183798, Feb 27, 2007

Filed:

Jan 24, 2005

Appl. No.:

11/041319

Inventors:

Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Claudia Stanley - Austin TX, US
John Schadt - Bethlehem PA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19/173

US Classification:

326 38, 326 93, 36523005

Abstract:

Systems and methods are disclosed herein to provide improved memory techniques for logic blocks within a programmable logic device. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a first and a second logic slice adapted to receive a first and a second clock signal. The first and second logic slices may be combined to form wider and deeper memory and single port or synchronous dual port memory.

US Patent:

7378872, May 27, 2008

Filed:

Jun 2, 2006

Appl. No.:

11/445620

Inventors:

Om P. Agrawal - Los Altos CA, US
Barry Britton - Orefield PA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19/177

US Classification:

326 41, 326 37, 326 38, 326 39, 326 47

Abstract:

Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks, with at least one of the programmable logic blocks having at least a first, a second, and a third logic block slice of different logic block slice types.

US Patent:

7385417, Jun 10, 2008

Filed:

Jun 2, 2006

Appl. No.:

11/446542

Inventors:

Om P. Agrawal - Los Altos CA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G06F 7/38
H03K 19/173

US Classification:

326 39, 326 41, 326 47

Abstract:

Systems and methods are disclosed herein to provide dual slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within each of the programmable logic blocks, wherein each dual-slice logic block includes a first and a second slice each having at least a first lookup table, with a first one of the dual-slice logic blocks of a logic block slice type different from a second one of the dual-slice logic blocks, and a third one of the dual-slice logic blocks of a logic block slice type different from the first and second dual-slice logic blocks.

US Patent:

7397276, Jul 8, 2008

Filed:

Jun 2, 2006

Appl. No.:

11/446351

Inventors:

Om P. Agrawal - Los Altos CA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19/177

US Classification:

326 41, 326 38, 326 39, 326 47

Abstract:

Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks, with each of the logic block slices having at least a first and a second slice each having at least a first lookup table. At least one of the programmable logic blocks includes at least a first logic block slice, a second logic block slice, and a third logic block slice, with the first logic block slice being a logic block slice type different from the second logic block slice, and the third logic block slice being a logic block slice type different from the first and second logic block slices. Control logic provides at a programmable logic block level bundled and/or unbundled control signals at a logic block slice level for at least two of the logic block slices.

US Patent:

7564716, Jul 21, 2009

Filed:

Nov 16, 2006

Appl. No.:

11/560554

Inventors:

Ronald J. Syzdek - Austin TX, US
David W. Chrudimsky - Austin TX, US
Xiaojie He - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 11/34

US Classification:

3651852, 36521001, 36521014

Abstract:

A read reference level of a plurality of read reference is determined for a set of bit cells of a non-volatile memory array. An indicator of the read reference level is stored in a non-volatile storage location associated with the set of bit cells. The indicator of the read reference level is accessed in response to a read access operation to the set of bit cells and a value stored at a memory location of the set of bit cells is sensed based on the indicator of the read reference level, whereby the memory location of the set of bit cells is associated with the read access operation.

US Patent:

7592834, Sep 22, 2009

Filed:

Jun 30, 2008

Appl. No.:

12/164265

Inventors:

Om P. Agrawal - Los Altos CA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19/173

US Classification:

326 38, 326 40, 326 41, 326 47

Abstract:

In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one programmable logic block includes a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register. The programmable logic block further includes control logic adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to configuration data stored within the configuration memory.