Xiaobing G Lee

US Patent:

7254175, Aug 7, 2007

Filed:

Jun 1, 2005

Appl. No.:

11/141955

Inventors:

Christopher Ward - Glen Ridge NJ, US
Clifford Pecota - New Egypt NJ, US
Xiaobing Lee - Nashua NH, US
Gary Hughes - Chelmsford MA, US

Assignee:

CrystalMedia Technology, Inc. - Sunnyvale CA

International Classification:

H04B 1/66

US Classification:

37524001, 37524025, 37524024, 37524026, 37524015, 382233, 382235, 382238, 382236

Abstract:

A method and apparatus for generating universal splice point adapters, where during a splicing operation an “out-point splicing adapter” is used to transition from an exit stream, while an “in-point splicing adapter” is used to transition to an entry stream.

US Patent:

7716566, May 11, 2010

Filed:

Jul 22, 2005

Appl. No.:

11/187737

Inventors:

Xiaobing Lee - Nashua NH, US
David J. Agans - Amherst NH, US
Bruce E. Mann - Mason NH, US

Assignee:

SeaChange International, Inc. - Acton MA

International Classification:

H03M 13/00

US Classification:

714821, 711114

Abstract:

Multiple corruptions and/or erasures in data storage or data communication systems are corrected. An encoder generates M of parity fields from N data channels. Each item of the generated parity fields is the result of simple exclusive-or operations on one item from one or more data fields and possibly one item from one or more of the other parity fields. A decoder can regenerate as many as M missing or corrupted fields of either data or parity using combinations of correct and/or previously corrected items as inputs using M independent parity equations to solve for and correct each missing or corrupted item in turn.

US Patent:

7882425, Feb 1, 2011

Filed:

Mar 22, 2010

Appl. No.:

12/728832

Inventors:

Xiaobing Lee - Nashua NH, US
David J. Agans - Amherst NH, US
Bruce E. Mann - Mason NH, US

Assignee:

Seachange International, Inc. - Acton MA

International Classification:

H03M 13/00

US Classification:

714821, 714804

Abstract:

Multiple corruptions and/or erasures in data storage or data communication systems are corrected. An encoder generates M of parity fields from N data channels. Each item of the generated parity fields is the result of simple exclusive-or operations on one item from one or more data fields and possibly one item from one or more of the other parity fields. A decoder can regenerate as many as M missing or corrupted fields of either data or parity using combinations of correct and/or previously corrected items as inputs using M independent parity equations to solve for and correct each missing or corrupted item in turn.

US Patent:

20190012259, Jan 10, 2019

Filed:

Jul 6, 2017

Appl. No.:

15/643404

Inventors:

- Plano TX, US
Xiaobing Lee - Santa Clara CA, US
Yunxiang Wu - Cupertino CA, US
Ken Hu - San Jose CA, US

International Classification:

G06F 12/02
G06F 12/0868

Abstract:

According to various aspects of the present disclosure, there is provided a method and an apparatus for writing and evicting data in a phase-change memory (PCM). In one embodiment, a logical block address (LBA) eviction candidate (LEC) list is stored in the PCM media. The LEC list employs a circular queue having a head end and tail end, where new LBAs are inserted at the head end. In one embodiment, a tail end LBA at the tail end of the LEC list along with all the subsequent LBAs on the LEC list with continuing write sequence number to that of the tail end LBA are evicted when data needs to be evicted from the PCM media.

US Patent:

20180225235, Aug 9, 2018

Filed:

Feb 3, 2017

Appl. No.:

15/424638

Inventors:

- Plano TX, US
Xiaobing Lee - Santa Clara CA, US

International Classification:

G06F 13/16
G06F 13/40
G06F 11/10

Abstract:

A hybrid DDR5 DIMM device includes a PCB board with a host interface through one of two DDR5 sub-channels, and a plurality of DDR4 or slow DDR5 SDRAM chips on the PCB coupled to this single channel DDR5 host interface. An embodiment processing system includes a host CPU to access a pairs of hybrid DDR5 DIMM devices for 4× DDR5 memory capacities (4DPC), a first or second hybrid DDR5 DIMM including a plurality of half-speed SDRAM chips, and a first or second DDR5 sub-channel coupled the host with slow SRAM chips on DIMM. Mounting same data-buffer and RCD chips on hybrid DIMM to a server motherboard can double available DDR4 DIMMs' speed to DDR5 speed rate. Pairs of hybrid DDR5 DIMM devices cascaded one-by-one can aggregate more DDR5 DIMM devices to expand memory capacities at double speed of DDR4 or DDR5 SDRAM chips, beyond current DDR5 speed limit 6400 MT/s.

US Patent:

20180060227, Mar 1, 2018

Filed:

Jan 31, 2017

Appl. No.:

15/420696

Inventors:

- Plano TX, US
Ken Hu - Santa Clara CA, US
Xiaobing Lee - Santa Clara CA, US
Yunxiang Wu - Santa Clara CA, US

International Classification:

G06F 12/02
G06F 12/122

Abstract:

A method performed by a processor to improve wear-leveling in a cross-point (XD) memory, comprises detecting, by a processor coupled to the XD memory, a trigger event, wherein the XD memory comprises a first section of memory units and a second section of memory units, and in response to detecting the trigger event, relocating, by the processor, data stored in a first memory unit of the first section of memory units to a memory unit adjacent to a last memory unit of the first section of memory units, and relocating, by the processor, data stored in a first memory unit of the second section of memory units to a memory unit adjacent to a last memory unit of the second section of memory units.

US Patent:

20160232112, Aug 11, 2016

Filed:

Feb 5, 2016

Appl. No.:

15/017522

Inventors:

- Plano TX, US
Xiaobing Lee - Santa Clara CA, US

International Classification:

G06F 13/16
G06F 13/40
G06F 3/06

Abstract:

A system including an unified memory interface (UMI) data bus and a method for operating the UMI bus are disclosed. In an embodiment, the system includes a UMI bus, a processor coupled to the UMI bus, a RAM/NVM device coupled to the UMI bus and NVM/SSD devices coupled to the UMI bus, wherein the UMI bus is configured to use RAM/NVM device random access waiting cycles to block access the NVM/SSD devices.

US Patent:

20160110126, Apr 21, 2016

Filed:

Jun 3, 2015

Appl. No.:

14/729817

Inventors:

- Plano TX, US
Xiaobing LEE - Santa Clara CA, US

International Classification:

G06F 3/06
G11C 11/56

Abstract:

A computer-implemented method for storing and caching data in an all-flash-array includes erasing a TLC-NAND flash cell and programming the cell with a binary value multiple times in sequence corresponding to multiple sequential stages between erasures. The method also includes processing the binary value in relation to a respective threshold voltage at each of the multiple sequential stages. The method further includes storing metadata corresponding to a current stage associated with the number of times the TLC-NAND flash cell has been programmed since being erased.