William Christopher Tanis

US Patent:

6714086, Mar 30, 2004

Filed:

Jan 11, 2001

Appl. No.:

09/758709

Inventors:

James Edward Landrith - Andover NJ
William J. Tanis - Wayne NJ

Assignee:

ITT Manufacturing Enterprises, Inc. - Wilmington DE

International Classification:

H03B 512

US Classification:

331 56, 331107 R, 331117 R, 331117 FE, 331177 V, 331 96, 331107 SL, 331167

Abstract:

A symmetrical oscillator includes a reactive element, such as an inductor, coupled between first and second active components, where the reactive element defines a fundamental resonant frequency with one or more capacitances of the oscillator. A first feedback circuit is coupled between the first active component and a common node, while a second feedback circuit is coupled between the second active component and the common node such that an output signal at substantially twice the fundamental resonant frequency is obtained at the common node.

US Patent:

52587207, Nov 2, 1993

Filed:

Mar 2, 1984

Appl. No.:

6/585651

Inventors:

William J. Tanis - Wayne NJ
Ning H. Lu - Parsippany NJ
Alan N. Schenberg - Kinnelon NJ

Assignee:

ITT Corporation - New York NY

International Classification:

H03D 1300

US Classification:

328133

Abstract:

The digital sample and hold phase detector to compare the phase relationship between input pulses and a high frequency reference clock comprises a digital counter arrangement coupled to count the high frequency reference clock to produce a digital ramp signal and a digital sampling arrangement coupled to at least the input pulses and an output of the counter arrangement to enable the input pulses to sample the digital ramp signal and produce a digital phase difference signal.

US Patent:

39597377, May 25, 1976

Filed:

Nov 18, 1974

Appl. No.:

5/524533

Inventors:

William J. Tanis - Wayne NJ

Assignee:

Engelmann Microwave Co. - Montville NJ

International Classification:

H03B 304

US Classification:

331 1A

Abstract:

A frequency synthesizer or portion thereof, that includes only one main phase-locked loop. The phase-lock loop includes a digital divider that can effectively divide in fractions, thus, permitting use of a higher reference frequency than normally required for the same degree of frequency resolution in integer divisor synthesizers. This, in turn, increases the short-term stability and reduces phase-noise. The fractional divider includes a secondary phase-lock loop that tends to introduce an unwanted ramp signal which causes spurious sidebands in the output signal. These spurious sidebands, when objectionable, are effectively suppressed by a circuit that generates a second ramp signal of similar frequency, duration and shape to the unwanted ramp signal but of opposite phase.

US Patent:

52587240, Nov 2, 1993

Filed:

Dec 30, 1983

Appl. No.:

6/566947

Inventors:

William J. Tanis - Wayne NJ
Ning H. Lu - Parsippany NJ
Alan N. Schenberg - Kinnelon NJ

Assignee:

ITT Corporation - New York NY

International Classification:

H03L 722
H03B 1900

US Classification:

331 1A

Abstract:

The fractional division frequency synthesizer comprises a digital ramp generator producing a digital correction ramp controlled by a frequency control programmer; a divide by N divider coupled to an output of a voltage controlled oscillator with the divider being controlled by the program, where N is a selected one of an integer and a fraction one or greater; a digital phase detector coupled to a reference clock and the output of the divider to provide a digital phase error signal; a digital adder coupled to an output of the ramp generator and the phase detector to produce a ramp corrected digital phase error signal; and circuit arrangement coupled to an output of the adder and a control input of the controlled oscillator to convert the ramp corrected digital phase error signal to a ramp corrected analog phase error signal to control the controlled oscillator and thereby provide a controlled frequency signal at the output thereof.