William Edward Pugh

US Patent:

20040062272, Apr 1, 2004

Filed:

Sep 30, 2002

Appl. No.:

10/261280

Inventors:

Gregory Greco - Frisco TX, US
William Pugh - Williamsburg VA, US
William Vivino - Wayne NJ, US

International Classification:

H04J003/16

US Classification:

370/466000, 370/411000

Abstract:

A method and architecture for transitioning the embedded base of Digital Loop Carrier access systems from the current narrowband circuit-switched paradigm—i.e., Synchronous Transfer Mode transport and Time division Multiplexed—to an Asynchronous Transfer Mode transport and ATM network interface paradigm. The invention operates to terminate the control data links from legacy DLC equipment, and to provide a protocol conversion function that enables these links to interface with the associated control and call processing structures of a serving packet switch. An additional function of the invention is the interfacing for bearer channels of the STM feeders from the legacy DLC and the provision of a Synchronous to Asynchronous Conversion function on such feeders.

US Patent:

40464547, Sep 6, 1977

Filed:

May 18, 1976

Appl. No.:

5/687463

Inventors:

William Edward Pugh - Lilburn GA

Assignee:

Bell Telephone Laboratories, Incorporated - Murray Hill NJ

International Classification:

G02B 516

US Classification:

350 96C

Abstract:

A thin chip having parallel, evenly spaced optical fiber-receiving grooves on at least one side forms the basic building block for a certain prior art multilayer optical fiber connector. The end arrays of fiber groups assembled within stacks of such chips are substantially identical in spacing, thus enabling a gang splice to be achieved with a simple abutment of the two end arrays. The present disclosure achieves vertical spacing between layers, as well as horizontal fiber spacing in a given layer, by including in the base of each chip a thin layer of compliant material to urge the fibers housed in the adjacent chip into their respective grooves. The compliance is sufficient to permit vertically adjacent chips to contact each other rather than to float atop fibers. The splice array additionally uses a key chip which rests upon a vertical reference surface with one end contacting a horizontal reference surface. These surfaces may form part of the permanent splice.

Author:

William Pugh

ISBN #:

3540428623