William Oliver Mathes

US Patent:

6657979, Dec 2, 2003

Filed:

Aug 23, 1999

Appl. No.:

09/379248

Inventors:

Lalit Odhavji Patel - Mesa AZ
William Oliver Mathes - Tempe AZ
Kevin Jurek - Gilbert AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04B 7185

US Classification:

370318, 370535, 370537

Abstract:

A multiplexer output cell (FIG. ) controls the operation of multiplexer input cells ( ) in a multistage multiplexer according to the value of a signal select input ( ), and a state control input ( ). A signal driver ( ) having a number of logical outputs comparable to the number of stages in the multiplexer is used in conjunction with the state control signal ( ) to control the power ON/OFF state of each cell in the multiplexer. The multiplexer input and output cells ( ) which are in the signal path are set to a power ON condition, while the multiplexer input and output cells ( ) which are not in the signal path are set to a power OFF position. In this manner, only those cells which are in the signal path are powered ON, resulting in significant power savings.

US Patent:

60207302, Feb 1, 2000

Filed:

Mar 22, 1999

Appl. No.:

9/273999

Inventors:

Kevin J. Jurek - Gilbert AZ
William O. Mathes - Tempe AZ
Lalit O. Patel - Mesa AZ

Assignee:

Motorola, Inc. - Schaunburg IL

International Classification:

G05F 312

US Classification:

323312

Abstract:

A method and apparatus for controlling current flow in current sources includes a current source FET (18), a control FET (20), and a driver circuit which includes complementary logic (310). The use of complementary logic for control advantageausly allows commonly available logic functions to control the current flow in individual current sources while maintaining a substantially constant bias voltage on the gate of the current source FETs. A chip-wide bias generator can be maintained substantially constant while controlling individual current sources.

US Patent:

56002602, Feb 4, 1997

Filed:

Jun 29, 1995

Appl. No.:

8/496651

Inventors:

Michael P. LaMacchia - Gilbert AZ
William O. Mathes - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 19003
H03K 1900

US Classification:

326 11

Abstract:

A method and apparatus for hardening current steering logic (CSL) to soft errors (charged particles passing through and upsetting the logic state of an integrated circuit) includes a hardened CSL circuit or cell (20), including three or more circuit cell elements (21) in parallel. The circuit cell elements (21) redundantly perform a single cell function. Each of the circuit cell elements (21) is coupled to soft error immune resistive elements (24 and 25) within a summing element (22). Current (23) is steered through the resistive elements (24 and 25) depending upon input signals (26) to each of the circuit cell elements (21). The logical output signal (27) is unaffected by a single soft error event since the majority of the total current (23) remains steered through the correct resistive element (24 or 25).

US Patent:

59492481, Sep 7, 1999

Filed:

Oct 2, 1997

Appl. No.:

8/943021

Inventors:

Michael Philip LaMacchia - Gilbert AZ
William Oliver Mathes - Tempe AZ
Bruce Alan Fette - Mesa AZ

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H03K 19003
H03K 1716

US Classification:

326 9

Abstract:

A single event upset (SEU) sensitivity control system (42) dynamically hardens a digital circuit (48) to single event upsets. The sensitivity control system (42) includes an upset rate sensor (66) for detecting a quantity of particles (38) that cause single event upsets. A noise margin control circuit (70) is configured to adjust a noise margin (46) of the digital circuit (48) in response to the quantity of particles (38). Noise margin (46) is increased when a particle density (34) is high to decrease the sensitivity of the digital circuit (48) to single event upsets. Additionally, noise margin (46) is decreased when a particle density (36) is low to decrease the power consumption level of digital circuit (48).