William E Crowther

Author:

William E. Crowther

ISBN #:

0275928403

Author:

William E. Crowther

ISBN #:

0814209122

US Patent:

50419714, Aug 20, 1991

Filed:

Nov 30, 1988

Appl. No.:

7/277993

Inventors:

Philip P. Carvey - Bedford MA
William R. Crowther - Lexington MA
Randall D. Rettberg - Concord MA

Assignee:

Bolt Beranek and Newman Inc. - Cambridge MA

International Classification:

G06F 1300
G06F 1516

US Classification:

364200

Abstract:

In parallel processing computational apparatus, a switching network employing both routing switch elements and concentrator elements efficiently couples bit serial messages from a multiplicity of processors to a multiplicity of memory modules. The apparatus operates in a highly synchronous mode in which all processors issue memory requests only at essentially the same predetermined time within a frame interval encompassing a predetermined substantial number of clock periods. The routing switch elements and concentrator elements incorporate circuitry for comparing the addresses of requests which may be blocked at any element with requests which get through and, if the addresses are the same, returning the memory response to all processors seeking the same memory location.

US Patent:

57517100, May 12, 1998

Filed:

Jun 11, 1996

Appl. No.:

8/661424

Inventors:

William R. Crowther - Lincoln MA
William P. Brandt - Groton MA

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 1200

US Classification:

370423

Abstract:

057517104 An efficient connection technique maximizes the rate at which data are transferred among source and destination network cards of a distributed network switch. Such maximum data rates are achieved by interconnecting the network cards through a mesh backplane comprising a novel arrangement of direct and indirect paths between the cards and thereafter transferring the data over those paths. In accordance with the invention, the indirect data path utilizes an additional network card of the switch as a 2-hop relay to provide transfer rate efficiency between the source and destination cards.

US Patent:

53943945, Feb 28, 1995

Filed:

Jun 24, 1993

Appl. No.:

8/081646

Inventors:

William R. Crowther - Lincoln MA
Stanley A. Lackey - Groton MA
C. Philip Levin - Malden MA
Daniel C. Tappan - Boxboro MA

Assignee:

Bolt Beranek and Newman Inc. - Cambridge MA

International Classification:

H04Q 1104
H04J 324

US Classification:

370 60

Abstract:

The classifier device disclosed herein analyzes message headers of the type which comprise a sequence of bit groups presented successively. The device employs a read/write memory for storing at a multiplicity of addresses, an alterable parse graph of instructions. The parse graph instructions include node instructions which comprise opcodes in association with respective next address characterizing data and terminator instructions which comprise identifying data for previously characterized header types. A logical processor responds to a node instruction read from memory either by initiating another memory read at a next address which, given the current state of the processor, is determinable from the current node instruction and the current header bit group or by outputting data indicating recognition failure if no next address is determinable. The logical processor responds to a terminator instruction by outputting respective header identifying data. Accordingly, for a previously characterized header type, a corresponding pattern of node instruction and a terminator instruction can be written into memory thereby enabling the device to identify the respective header type in a time which is essentially proportional to the length of the header and thus also to the time of presentation of the header.

US Patent:

41308654, Dec 19, 1978

Filed:

Oct 6, 1975

Appl. No.:

5/620131

Inventors:

Frank E. Heart - Lincoln MA
Severo M. Ornstein - Waban MA
William B. Barker - Maynard MA
William R. Crowther - Arlington MA

Assignee:

Bolt Beranek and Newman Inc. - Cambridge MA

International Classification:

G06F 918
G06F 1516

US Classification:

364200

Abstract:

Computer apparatus which employs a plurality of processing units, a memory unit, and a communication unit, each of the units including a data transfer bus. A bus coupler is provided between each pair of units of differing type to form a distributed data communications network. An addressable, passive task register is associated with one of the units for communication through the couplers and is adapted to register a task priority value associated with a task request, the register being readable by any one of the processor units to obtain the highest priority value registry.

Address:

1601 Old Tpke Rd, Oakham, MA 01068

Phone:

508 882-3152

VIN:

JTDKN3DU3C5419587

Make:

TOYOTA

Model:

PRIUS

Year:

2012