Whitney L West

US Patent:

20120235106, Sep 20, 2012

Filed:

Mar 17, 2011

Appl. No.:

13/050725

Inventors:

Sanh D. Tang - Boise ID, US
Scott E. Sills - Boise ID, US
Whitney L. West - Boise ID, US
Rob B. Goodwin - Eagle ID, US
Nishant Sinha - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

H01L 45/00
H01L 21/8239
H01L 21/4763

US Classification:

257 2, 438648, 438104, 257E21645, 257E45003, 257E21495

Abstract:

Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

US Patent:

20130320291, Dec 5, 2013

Filed:

Aug 7, 2013

Appl. No.:

13/961479

Inventors:

Scott E. Sills - Boise ID, US
Whitney L. West - Boise ID, US
Rob B. Goodwin - Eagle ID, US
Nishant Sinha - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 45/00

US Classification:

257 4, 438382

Abstract:

Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

US Patent:

20190363253, Nov 28, 2019

Filed:

Aug 12, 2019

Appl. No.:

16/538477

Inventors:

- Boise ID, US
Scott E. Sills - Boise ID, US
Whitney L. West - Boise ID, US
Rob B. Goodwin - Eagle ID, US
Nishant Sinha - Boise ID, US

International Classification:

H01L 45/00
H01L 21/768
H01L 23/532

Abstract:

Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

US Patent:

20180114901, Apr 26, 2018

Filed:

Dec 20, 2017

Appl. No.:

15/848399

Inventors:

- Boise ID, US
Scott E. Sills - Boise ID, US
Whitney L. West - Boise ID, US
Rob B. Goodwin - , US
Nishant Sinha - Boise ID, US

International Classification:

H01L 45/00
H01L 21/768
H01L 23/532

Abstract:

Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

US Patent:

20170092855, Mar 30, 2017

Filed:

Dec 12, 2016

Appl. No.:

15/375457

Inventors:

- Boise ID, US
Scott E. Sills - Boise ID, US
Whitney L. West - Boise ID, US
Rob B. Goodwin - Eagle ID, US
Nishant Sinha - Boise ID, US

International Classification:

H01L 45/00

Abstract:

Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.