Wenjuan Zhu

US Patent:

7504700, Mar 17, 2009

Filed:

Apr 21, 2005

Appl. No.:

10/907935

Inventors:

Wenjuan Zhu - Carmel NY, US
Michael P. Chudzik - Danbury CT, US
Oleg Gluschenkov - Poughkeepsie NY, US
Akihisa Sekiguchi - Briarcliff Manor NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/088
H01L 21/3205
H01L 21/4763

US Classification:

257410, 438591, 438287

Abstract:

A semiconductor structure and method of forming the same, comprising forming a uniform buffer layer of diffusion-controlling stable material on top of a base gate dielectric layer, and then forming a uniform layer which contains a source of transitional metal atoms, and then annealing the structure to diffuse the transitional metal atoms from their source through the diffusion-controlling material and into the base gate dielectric layer.

US Patent:

7528027, May 5, 2009

Filed:

Mar 25, 2008

Appl. No.:

12/054727

Inventors:

Huilong Zhu - Poughkeepsie NY, US
Mahender Kumar - Fishkill NY, US
Dan M. Mocuta - LaGrangeville NY, US
Ravikumar Ramachandran - Pleasantville NY, US
Wenjuan Zhu - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336

US Classification:

438197, 438149, 438151, 438158, 438199, 438264, 438268, 257209, 257255, 257347, 257365, 257E21249

Abstract:

An SOI CMOS structure includes a v-shape trench in a pFet region. The v-shape trench has a surface in a (111) plane and extends into an SOI layer in the pFet region. A layer, such as a gate oxide or high-k material, is formed in the v-shape trench. Poly-Si is deposited on top of the layer.

US Patent:

7718513, May 18, 2010

Filed:

Apr 13, 2007

Appl. No.:

11/734888

Inventors:

Huilong Zhu - Poughkeepsie NY, US
Wenjuan Zhu - Carmel NY, US
Zhijiong Luo - Carmel NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/20

US Classification:

438478, 438243, 438386

Abstract:

Methods of forming silicided contacts self-aligned to a gate from polysilicon germanium and a structure so formed are disclosed. One embodiment of the method includes: forming a polysilicon germanium (poly SiGe) pedestal over a gate dielectric over a substrate; forming a poly SiGe layer over the poly SiGe pedestal, the poly SiGe layer having a thickness greater than the poly SiGe pedestal; doping the poly SiGe layer; simultaneously forming a gate and a contact to each side of the gate from the poly SiGe layer, the gate positioned over the poly SiGe pedestal; annealing to drive the dopant from the gate and the contacts into the substrate to form a source/drain region below the contacts; filling a space between the gate and the contacts; and forming silicide in the gate and the contacts.

US Patent:

8101474, Jan 24, 2012

Filed:

Jan 6, 2010

Appl. No.:

12/652804

Inventors:

Wenjuan Zhu - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/338
H01L 29/66

US Classification:

438175, 438591, 257216, 257E21409, 257E29049

Abstract:

A novel buried-channel graphene device structure and method for manufacture. The new structure includes a two level channel layer comprised of a buried-channel graphene layer with an amorphous silicon top channel layer. The method for making such structure includes the steps of depositing a graphene layer on a substrate, depositing an amorphous silicon layer on the graphene layer, converting the upper layer of the amorphous silicon layer to a gate dielectric by nitridation, oxidation or oxynitridation, while keeping the lower layer of the amorphous silicon layer to serve as part of the channel to form the buried-channel graphene device.

US Patent:

8519450, Aug 27, 2013

Filed:

Aug 17, 2012

Appl. No.:

13/588906

Inventors:

Wenjuan Zhu - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/84

US Classification:

257254, 257252, 257E27085, 977734, 365157

Abstract:

Embodiments relate to a graphene-based memory device. The graphene-based memory device includes a first graphene layer and a second graphene layer. A first insulation layer is located between the first and second graphene layers. The first insulation layer has an opening between the first and second graphene layers, and the first graphene layer is configured to bend into the opening to contact the second graphene layer based on a first electrostatic force.

US Patent:

8530886, Sep 10, 2013

Filed:

Mar 18, 2011

Appl. No.:

13/051707

Inventors:

Phaedon Avouris - Yorktown Heights NY, US
Deborah A. Neumayer - Danbury CT, US
Wenjuan Zhu - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/12

US Classification:

257 29, 257E51006, 257E51038, 977938

Abstract:

A semiconductor structure which includes a substrate; a graphene layer on the substrate; a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension; a nitride layer on the graphene layer between the source electrode and drain electrode; and a gate electrode on the nitride layer, wherein the nitride layer is a gate dielectric for the gate electrode.

US Patent:

8557686, Oct 15, 2013

Filed:

Aug 27, 2012

Appl. No.:

13/595498

Inventors:

Wenjuan Zhu - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/20

US Classification:

438479, 257254, 257E27085, 977734

Abstract:

Embodiments relate to a method of forming a graphene-based memory device. The method includes forming a forming a first graphene layer on an first insulator layer, and forming a second insulation layer on the first graphene layer. The method further includes forming a second graphene layer on the second insulation layer and forming an opening in the second insulation layer to expose a portion of the first graphene layer and a portion of the second graphene layer and to suspend the exposed portion of the second graphene layer in the opening.

US Patent:

8564027, Oct 22, 2013

Filed:

Jan 27, 2012

Appl. No.:

13/359647

Inventors:

Wenjuan Zhu - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/84

US Classification:

257254, 257252, 257E27085, 977734, 365157

Abstract:

Semiconductor nano-devices, such as nano-probe and nano-knife devices, which are constructed using graphene films that are suspended between open cavities of a semiconductor structure. The suspended graphene films serve as electro-mechanical membranes that can be made very thin, from one or few atoms in thickness, to greatly improve the sensitivity and reliability of semiconductor nano-probe and nano-knife devices.