Marvell Semiconductor
Principal Engineer -- Design For Test
Marvell Semiconductor
Principal Engineer, Technical Marketing and Business Development
Marvell Semiconductor Mar 2006 - Jul 2013
Asic Project Manager
Avago Technologies Nov 2005 - Mar 2006
Asic Project Manager
Agilent Technologies May 2000 - Nov 2005
Design-For-Test, Asic Design Lead and Project Manager
Education:
University of Idaho 1998 - 2000
University of Idaho 1991 - 1995
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering
Skills:
Asic Integrated Circuit Design Verilog Dft Testing Vhdl Semiconductors Application Specific Integrated Circuits Soc Synopsys Tools Perl Analog Simulations Ic System on A Chip C Silicon Debugging Cadence Integrated Circuits
Walter Lee McNall - Meridian ID, US Randall D. Briggs - Boise ID, US
Assignee:
Marvell International Ltd.
International Classification:
G06K 15/00 G06F 3/12
US Classification:
358 116, 358 113
Abstract:
A system and method are disclosed for updating data stored in a one-time programmable (non-rewritable) non-volatile storage device (“OTP”). The OTP is segmented so that updated data may be written to unused areas. Valid data may be differentiated from stale data using a data recognition technique such as tallying or indexing. According to a tallying technique, an updated event count may be obtained by counting the number of blown bits in the OTP. Each time the event occurs, the next bit is blown. According to an indexing technique, each bit in an index corresponds to a data block in the OTP. When updated data is written to the next (empty) data block in order in the OTP, the corresponding (next) index bit is blown. A valid data set may be located by counting the number of blown bits in the index.
Regulating An Operating Condition Of An Integrated Circuit To Compensate For A Manufacturing Variation
Randall D. Briggs - Boise ID, US Eran Maor - Nes-Ziona, IL Walter Lee McNall - Meridian ID, US William B. Weiser - Meridian ID, US Haggai Telem - Moshav Lachish, IL
Assignee:
Marvell International Ltd. - Hamilton Marvell Israel (MISL) Ltd. - Yokneam
International Classification:
H03L 7/081
US Classification:
331 25, 327161, 327291, 331 1 R
Abstract:
An integrated circuit has operational circuitry to perform an operation. An operational regulator regulates an operating condition of the operational circuitry. The operational regulator has a sample clock to generate a sample clock signal. The sample clock signal correlates to a manufacturing variation of the electronic circuitry. The operational regulator also includes a configurator to evaluate the sample clock signal and generate a configuration signal according to the evaluation. A controller is provided to receive the configuration signal and control an operating condition of the operational circuitry according to the configuration signal.
Method And Apparatus For Authenticating A Semiconductor Die
- St. Michael, BB Walter Lee McNall - Meridian ID, US Robert W. Shreeve - Corvallis OR, US Thomas Page Bruch - Corvallis OR, US Neal C. Jaarsma - Corvallis OR, US
International Classification:
H01L 21/268 H01L 21/768 H03K 19/177
US Classification:
326 8, 438795, 438467
Abstract:
The present disclosure describes apparatuses and techniques for device-based die authentication. In some aspects, an intensity of a particle beam is varied during semiconductor processing to provide a semiconductor die having devices of varied values. In other aspects, different areas of semiconductor dies are exposed during semiconductor processing to provide semiconductor dies with devices that vary in value from one die to the next. For each semiconductor die, a value generated based on the values of the die's respective devices can be associated with that die thereby enabling subsequent authentication of the semiconductor die.