Vladimir F Drobny

US Patent:

6335558, Jan 1, 2002

Filed:

May 17, 2000

Appl. No.:

09/573032

Inventors:

Vladimir F. Drobny - Tucson AZ
Kevin Bao - Tucson AZ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 27082

US Classification:

257591, 257574, 257592

Abstract:

An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850Â C. As the substrate is heated to a temperature of 1050Â C. , N+ dopant gas is injected into the carrier gas to suppress autodoping due to P+ atoms that escape from the P+ buried layer regions. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080Â C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080Â C. Then an N- epitaxial layer is deposited on the second cap layer at 1080Â C.

US Patent:

6576535, Jun 10, 2003

Filed:

Apr 11, 2001

Appl. No.:

09/829897

Inventors:

Vladimir F. Drobny - Tucson AZ
Dennis D. Liu - Tucson AZ

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2020

US Classification:

438507, 438503, 438203, 438322, 438481, 438542

Abstract:

A method for fabricating a high speed complementary bipolar/CMOS device is disclosed which enables the forming of a silicon epitaxial layer in a PNP transistor having carbon incorporated therein to suppress boron up-diffusion from lower heavily boron-doped buried layers into upper PNP structures. According to an embodiment of the invention, an epitaxial layer is formed on a P type silicon substrate in which a plurality of P buried layer regions, a plurality of N buried layer regions, and a P field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas and pre-baked at a temperature of approximately 850Â C. for a time. The temperature is then increased to approximately 1050Â C. and subjected to a high temperature bake cycle.

US Patent:

7202533, Apr 10, 2007

Filed:

Sep 29, 2005

Appl. No.:

11/239253

Inventors:

Eric W. Beach - Tucson AZ, US
Vladimir F. Drobny - Tucson AZ, US
Derek W. Robinson - Tucson AZ, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/62

US Classification:

257363, 257358, 257516, 257E27016, 257E27035, 257E27047, 438358, 438384

Abstract:

An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor, and a second thin film resistor disposed on the second dielectric layer. A first layer of interconnect conductors is disposed on the second dielectric layer and includes a first interconnect conductor contacting a first contact area of the first thin film resistor, a second interconnect conductor contacting a second contact area of the first thin film resistor, and a third interconnect conductor electrically contacting a first contact area of the second thin film resistor. A third dielectric layer is disposed on the second dielectric layer. A second layer of interconnect conductors is disposed on the third dielectric layer including a fourth interconnect conductor for contacting the second interconnect conductor.

US Patent:

7388271, Jun 17, 2008

Filed:

Jul 1, 2005

Appl. No.:

11/174190

Inventors:

Vladimir Drobny - Tucson AZ, US
Derek Robinson - Tucson AZ, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 27/095
H01L 29/47
H01L 29/812
H01L 31/07
H01L 31/108

US Classification:

257475, 257476, 257485, 257E29148, 257E29338

Abstract:

A method of forming a rectifying diode. The method comprises providing a first semiconductor region of a first conductivity type and having a first dopant concentration and forming a second semiconductor region in the first semiconductor region. The second semiconductor region has the first conductivity type and having a second dopant concentration greater than the first dopant concentration. The method also comprises forming a conductive contact to the first semiconductor region and forming a conductive contact to the second semiconductor region. The rectifying diode comprises a current path, and the path comprises: (i) the conductive contact to the first semiconductor region; (ii) the first semiconductor region; (iii) the second semiconductor region; and (iv) the conductive contact to the second semiconductor region. The second semiconductor region does not extend to a layer buried relative to the first semiconductor region.

US Patent:

7416951, Aug 26, 2008

Filed:

Sep 29, 2005

Appl. No.:

11/238715

Inventors:

Eric W. Beach - Tucson AZ, US
Vladimir F. Drobny - Tucson AZ, US
Derek W. Robinson - Tucson AZ, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8222

US Classification:

438330, 438384, 257E21004

Abstract:

An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer. A second thin film resistor is formed on the second dielectric layer. A third dielectric layer is formed on the second dielectric layer. A second layer of interconnect conductors on the third dielectric layer includes a third interconnect conductor extending through an opening in the second and third dielectric layers to contact the first interconnect conductor, a fourth interconnect conductor extending through an opening in the second and third dielectric layers to contact the second interconnect conductor, and two interconnect conductors extending through openings in the third dielectric layer of the second thin film resistor. A fifth interconnect conductor extends through an opening in the first dielectric layer to contact a circuit element.

US Patent:

7964919, Jun 21, 2011

Filed:

Jul 21, 2008

Appl. No.:

12/176612

Inventors:

Eric W. Beach - Tuscon AZ, US
Vladimir F. Drobny - Tuscon AZ, US
Derek W. Robinson - Tuscon AZ, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 27/11

US Classification:

257379, 257382, 257E27035

Abstract:

An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer. A second thin film resistor is formed on the second dielectric layer. A third dielectric layer is formed on the second dielectric layer. A second layer of interconnect conductors on the third dielectric layer includes a third interconnect conductor extending through an opening in the second and third dielectric layers to contact the first interconnect conductor, a fourth interconnect conductor extending through an opening in the second and third dielectric layers to contact the second interconnect conductor, and two interconnect conductors extending through openings in the third dielectric layer of the second thin film resistor. A fifth interconnect conductor extends through an opening in the first dielectric layer to contact a circuit element.

US Patent:

8030155, Oct 4, 2011

Filed:

May 12, 2008

Appl. No.:

12/119087

Inventors:

Vladimir F. Drobny - Tucson AZ, US
Derek W. Robinson - Tucson AZ, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/329
H01L 29/872

US Classification:

438237, 438571, 257379, 257476, 257528, 257E21359, 257E29338

Abstract:

A method of forming a rectifying diode. The method comprises providing a first semiconductor region of a first conductivity type and having a first dopant concentration and forming a second semiconductor region in the first semiconductor region. The second semiconductor region has the first conductivity type and having a second dopant concentration greater than the first dopant concentration. The method also comprises forming a conductive contact to the first semiconductor region and forming a conductive contact to the second semiconductor region. The rectifying diode comprises a current path, and the path comprises: (i) the conductive contact to the first semiconductor region; (ii) the first semiconductor region; (iii) the second semiconductor region; and (iv) the conductive contact to the second semiconductor region. The second semiconductor region does not extend to a layer buried relative to the first semiconductor region.

US Patent:

8053322, Nov 8, 2011

Filed:

Dec 29, 2008

Appl. No.:

12/344995

Inventors:

Vladimir F. Drobny - Tucson AZ, US
Amitava Chatterjee - Plano TX, US
Phillipp Steinmann - Richardson TX, US
Rick Wise - Fairview TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/336

US Classification:

438296, 438770, 257E2155, 257E21301

Abstract:

A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric layers generally 500 to 5,000 Angstroms thick. The method includes providing a substrate having a silicon including surface. A plurality of dielectric filled trench isolation regions are formed in the substrate. The silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. An epitaxial silicon comprising layer is deposited, wherein the epitaxial comprising silicon layer is formed over the silicon comprising surface. The epitaxial comprising silicon layer is oxidized to convert at least a portion into a thermally grown silicon oxide layer, wherein the thermally grown silicon oxide layer provides at least a portion of a gate dielectric layer for at least one of said plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges.