Vincent T Bocchino

US Patent:

6651155, Nov 18, 2003

Filed:

Jul 30, 2001

Appl. No.:

09/918907

Inventors:

Vincent T. Bocchino - San Mateo CA
Colin Hendry - Maidenhead Berks, GB
Stephane Cauneau - London, GB
Virendra Patel - Wembley, GB

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1200

US Classification:

711202, 711103

Abstract:

A circuit for translating a configuration file used to configure a programmable logic device includes a first register to serially receive configuration data. A second register receives, in parallel, configuration data from the first register. A translation address memory translates an original address for a selected configuration bit of the configuration data to a translated address. A translation memory stores the selected configuration bit at the translated address. Control logic selectively downloads configuration data from the translation memory to a programmable logic device core.

US Patent:

62081624, Mar 27, 2001

Filed:

Feb 19, 1998

Appl. No.:

9/026885

Inventors:

Vincent T. Bocchino - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K19/173

US Classification:

326 38

Abstract:

A technique for configuring programmable integrated circuits. The technique involves preconditioning or predefining the outputs and I/Os of a programmable integrated circuit before the device is programmed or reconfigured. When the device is programmed, the outputs and I/Os of the programmable integrated circuit will be driven to the preconditioned or predefined states. The technique may be implemented in conformance with the IEEE 1149. 1 boundary scan architecture standard. Standard IEEE 1149. 1 instructions may be used. The technique may also be used during in-system programming of programmable integrated circuits.

US Patent:

58699791, Feb 9, 1999

Filed:

May 9, 1996

Appl. No.:

8/647102

Inventors:

Vincent T. Bocchino - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 38

Abstract:

A technique for configuring programmable integrated circuits. The technique involves preconditioning or predefining the outputs and I/Os of a programmable integrated circuit before the device is programmed or reconfigured. When the device is programmed, the outputs and I/Os of the programmable integrated circuit will be driven to the preconditioned or predefined states. The technique may be implemented in conformance with the IEEE 1149. 1 boundary scan architecture standard. Standard IEEE 1149. 1 instructions may be used. The technique may also be used during in-system programming of programmable integrated circuits.