Vikas R Amrelia

US Patent:

6388315, May 14, 2002

Filed:

Aug 29, 2001

Appl. No.:

09/941829

Inventors:

Lawrence T. Clark - Phoenix AZ
Vikas R. Amrelia - Gilbert AZ
Raphael A. Soetan - Chandler AZ
Eric J. Hoffman - Chandler AZ
Tuan X. Do - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2352

US Classification:

257691, 257356, 257357

Abstract:

An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

US Patent:

RE42776, Oct 4, 2011

Filed:

May 23, 2007

Appl. No.:

11/802556

Inventors:

Lawrence T. Clark - Phoenix AZ, US
Vikas R. Amrelia - Gilbert AZ, US
Raphael A. Soetan - Chandler AZ, US
Eric J. Hoffman - Chandler AZ, US
Tuan X. Do - Chandler AZ, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H01L 23/52

US Classification:

257691, 257204, 257206, 257207, 257208, 257369, 257371, 257E2163, 257E27107, 257E27108, 257E27067, 257355, 257356, 257357, 257358, 257360, 257363, 257291, 257338

Abstract:

An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

US Patent:

RE43326, Apr 24, 2012

Filed:

May 24, 2007

Appl. No.:

11/802763

Inventors:

Lawrence T. Clark - Phoenix AZ, US
Vikas R. Amrelia - Gilbert AZ, US
Raphael A. Soetan - Chandler AZ, US
Eric J. Hoffman - Chandler AZ, US
Tuan X. Do - Chandler AZ, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H01L 21/20

US Classification:

438395, 438393, 438394, 361637, 361638, 361639, 307 58, 307147, 307148

Abstract:

An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

US Patent:

20020026261, Feb 28, 2002

Filed:

Aug 29, 2001

Appl. No.:

09/941489

Inventors:

Lawrence Clark - Phoenix AZ, US
Vikas Amrelia - Gilbert AZ, US
Raphael Soetan - Chandler AZ, US
Eric Hoffman - Chandler AZ, US
Tuan Do - Chandler AZ, US

International Classification:

G06F019/00

US Classification:

700/121000

Abstract:

An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

US Patent:

6368933, Apr 9, 2002

Filed:

Dec 15, 1999

Appl. No.:

09/464023

Inventors:

Lawrence T. Clark - Phoenix AZ
Vikas R. Amrelia - Gilbert AZ
Raphael A. Soetan - Chandler AZ
Eric J. Hoffman - Chandler AZ
Tuan X. Do - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2120

US Classification:

438395, 438393, 438394, 361637, 361638, 361639, 307 58, 307147, 307148

Abstract:

An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.