Victor Ivan Torres

US Patent:

7332403, Feb 19, 2008

Filed:

Jul 11, 2005

Appl. No.:

11/179022

Inventors:

Rodney Hill - Mansfield TX, US
Victor Torres - Irving TX, US
William Max Coppock - Arlington TX, US
Terry L. Lines - Mansfield TX, US
Tom Bold - Roanoke TX, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21/20

US Classification:

438382, 438384, 257E27047

Abstract:

A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. A layer of dielectric material is formed over the resistor protect layer. The dielectric material is masked and dry etched to leave a first portion of dielectric material over a first end of the thin film resistor and a second portion of dielectric material over a second end of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the dielectric material as a hard mask. Then a second dielectric layer is deposited and vias are etched down to the underlying portions of the resistor protect layer.

US Patent:

7410879, Aug 12, 2008

Filed:

Aug 3, 2005

Appl. No.:

11/196787

Inventors:

Rodney Hill - Mansfield TX, US
Victor Torres - Irving TX, US
Michael Burger - Arlington TX, US
Terry L. Lines - Mansfield TX, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21/20

US Classification:

438384

Abstract:

A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. First and second portions of a first dielectric material are formed over the resistor protect layer over the first and second ends of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the first dielectric material as a hard mask. Then a second dielectric layer is deposited. A first via mask and etch process is used to etch vias down to the underlying portions of the resistor protect layer over the ends of the thin film resistor. A second via mask and etch process is used to etch substrate vias to an underlying conductor layer.

US Patent:

7456097, Nov 25, 2008

Filed:

Nov 30, 2004

Appl. No.:

10/999542

Inventors:

Rodney Hill - Mansfield TX, US
Victor M. Torres - Irving TX, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21/4763

US Classification:

438637, 438640, 257E21577, 257E21578

Abstract:

A system and method is disclosed for providing an etch procedure to facet the top corners of a via in a semiconductor device. A vertical anisotropic dry etch process is applied through an aperture in a resist mask to etch through a dielectric layer down to a bottom conductor layer. The resist mask is removed and an etch process is applied to etch away corner portions of the dielectric layer. The etch process forms a flat sidewall surface in the portions of the dielectric layer that form the via. The flat sidewall surface is disposed at an obtuse angle with respect to the top surface of the dielectric layer and at an obtuse angle with respect to a vertical sidewall of the via cavity. The flat sidewall surface and the absence of sharp corners facilitate a subsequent metal fill process.

US Patent:

7585775, Sep 8, 2009

Filed:

Nov 21, 2005

Appl. No.:

11/285702

Inventors:

Thomas Bold - Roanoke TX, US
Victor Torres - Irving TX, US
Rodney Hill - Mansfield TX, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21/302
H01L 21/461

US Classification:

438706, 438710, 438714, 438717, 438723, 438725

Abstract:

A method is disclosed for applying a plasma etch process to facet a masking layer in a semiconductor device by creating sloped surfaces in the masking layer. The masking layer is plasma etched with a plasma that has a high sputter etch component. The plasma etch process removes material from vertical edges of the masking layer to form a sloped surface at each vertical edge of the masking layer. A layer of conductive material is then applied to the masking layer. When the layer of conductive material is subsequently removed by an overetch process the sloped profile of the masking layer facilitates the removal of stringers of conductive material without using an excessively lengthy overetch.

US Patent:

7808048, Oct 5, 2010

Filed:

Oct 15, 2007

Appl. No.:

11/974647

Inventors:

Rodney Hill - Mansfield TX, US
Victor Torres - Irving TX, US
William Max Coppock - Arlington TX, US
Terry L. Lines - Mansfield TX, US
Tom Bold - Roanoke TX, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 23/62

US Classification:

257358, 257359, 257379, 257E27047

Abstract:

A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. A layer of dielectric material is formed over the resistor protect layer. The dielectric material is masked and dry etched to leave a first portion of dielectric material over a first end of the thin film resistor and a second portion of dielectric material over a second end of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the dielectric material as a hard mask. Then a second dielectric layer is deposited and vias are etched down to the underlying portions of the resistor protect layer.

US Patent:

7960240, Jun 14, 2011

Filed:

Jul 9, 2008

Appl. No.:

12/217877

Inventors:

Rodney Hill - Mansfield TX, US
Victor Torres - Irving TX, US
Michael Burger - Arlington TX, US
Terry L. Lines - Mansfield TX, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21/20

US Classification:

438382, 438618, 438620, 438622

Abstract:

A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. First and second portions of a first dielectric material are formed over the resistor protect layer over the first and second ends of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the first dielectric material as a hard mask. Then a second dielectric layer is deposited. A first via mask and etch process is used to etch vias down to the underlying portions of the resistor protect layer over the ends of the thin film resistor. A second via mask and etch process is used to etch substrate vias to an underlying conductor layer.

US Patent:

20130017203, Jan 17, 2013

Filed:

Jun 19, 2012

Appl. No.:

13/527436

Inventors:

Victor J. TORRES - New York NY, US
Francis ALONZO, III - New York NY, US

Assignee:

NEW YORK UNIVERSITY - New York NY

International Classification:

A61K 39/40
A61K 39/385
A61K 31/7088
A61K 38/02
A61K 31/724
C12Q 1/68
G01N 33/566
G01N 21/75
G01N 21/64
C12Q 1/02
A61P 37/04
A61P 31/04
A61P 17/02
A61P 19/08
A61P 17/00
A61P 19/02
A61P 9/00
A61P 29/00
A61K 39/085

US Classification:

4241391, 4242371, 4241901, 42419711, 4241651, 4241581, 514 44 R, 514 27, 514 58, 435 615, 435 71, 435 29, 435 61

Abstract:

The present invention relates to methods and compositions for preventing and treating in a subject. Therapeutic compositions of the present invention comprise leukocidin E and/or D proteins or polypeptides and anti-leukocidin E and/or D antibodies. The invention further relates to methods of identifying inhibitors of LukE/D cytotoxicity and inhibitors of LukE/D-leukocyte binding.

US Patent:

20130039885, Feb 14, 2013

Filed:

Jun 19, 2012

Appl. No.:

13/527438

Inventors:

Victor J. TORRES - New York NY, US
Derya UNUTMAZ - New York NY, US
Francis ALONZO, III - New York NY, US

Assignee:

NEW YORK UNIVERSITY - New York NY

International Classification:

A61K 38/16
A61P 31/18
A61P 29/00
A61P 19/02
A61P 17/06
A61P 9/10
A61P 1/00
A61P 1/04
A61P 25/00
A61P 3/10
A61P 1/16
A61P 19/04
A61P 31/06
A61P 31/00
A61P 19/08
A61P 37/06
A61K 31/46
A61P 31/04
A61K 31/506
A61K 39/395
A61K 31/351
A61K 38/20

US Classification:

424 852, 514 38, 514 11, 514 212, 514 166, 514 187, 514 19, 514 132, 514 179, 514 69, 514 24, 514 23, 514 167, 514 177, 514304, 51425218, 4241431, 514459

Abstract:

The present invention relates to methods for preventing or treating Human Immunodeficiency Virus (HIV) infection, inflammatory conditions, and graft-versus-host-disease (GVHD) in a subject. Therapeutic compositions of the present invention comprise Leukocidin E (LukE) and/or D proteins or polypeptides. The invention further relates to methods of treating infection by administering a composition comprising a CCR5 antagonist or any molecule that blocks LukE/D interaction with CCR5 cells in an amount effective to treat the infection in the subject.

Author:

Victor Torres

ISBN #:

0871235161

Author:

Victor Torres

ISBN #:

8479351950

Author:

Victor Torres

ISBN #:

8479354941

Author:

Victor M. Torres

ISBN #:

8473800400