Venu Madha Kuchibhotla

US Patent:

7254730, Aug 7, 2007

Filed:

Feb 14, 2003

Appl. No.:

10/367076

Inventors:

James Kardach - Saratoga CA, US
Jeffrey Huckins - Chandler AZ, US
Kristoffer Fleming - Chandler AZ, US
Brian Belmont - Portland OR, US
Pochang Hsu - Fremont CA, US
Venu Kuchibhotla - Campbell CA, US
Richard Forand - Portland OR, US
Uma Gadamsetty - Chandler AZ, US
Gunner Danneels - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26

US Classification:

713323, 713300, 713320, 713321, 713324

Abstract:

A method and apparatus for a user to interface with a mobile computing device is disclosed. In one embodiment, a method, comprises providing information on a user interface connected to a mobile computing device having a primary display, wherein the mobile computing device can be operated in multiple power states, and the user interface does not include the primary display.

US Patent:

7348957, Mar 25, 2008

Filed:

Feb 14, 2003

Appl. No.:

10/367070

Inventors:

Ying Cui - Mountain View CA, US
Richard W. Jensen - Fair Oaks CA, US
David Wyatt - San Jose CA, US
Venu M. Kuchibhotla - Campbell CA, US
Sathyamurthi Sadhasivan - Eldorado Hills CA, US
Todd M. Witter - Orangevale CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G09G 3/28

US Classification:

345102, 345 63, 345207, 345211, 345212

Abstract:

According to one embodiment of the present invention, a method of power management for a flat panel display is disclosed. The method includes: receiving image data; determining a segment mode for the received image data; selecting a portion of the received image data corresponding to the determined segment mode; accumulating a value of the selected portion of the received image data; comparing the accumulated value to a threshold value; and generating an interrupt signal if the accumulated value exceeds the threshold value.

US Patent:

8621159, Dec 31, 2013

Filed:

Feb 3, 2010

Appl. No.:

13/148665

Inventors:

Frederick A. Ware - Los Altos Hills CA, US
John E. Linstadt - Palo Alto CA, US
Venu M. Kuchibhotla - Campbell CA, US

Assignee:

Rambus Inc. - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711148, 711103, 711105, 711149, 711150

Abstract:

A memory device loops back control information from one interface to another interface to facilitate sharing of the memory device by multiple devices. In some aspects, a memory controller sends control and address information to one interface of a memory device when accessing the memory device. The memory device may then loop back this control and address information to another interface that is used by another memory controller to access the memory device. The other memory controller may then use this information to determine how to access the memory device. In some aspects a memory device loops back arbitration information from one interface to another interface thereby enabling controller devices that are coupled to the memory device to control (e. g. , schedule) accesses of the memory device.

US Patent:

20120221769, Aug 30, 2012

Filed:

Jul 14, 2009

Appl. No.:

13/054910

Inventors:

Frederick A. Ware - Los Altos Hills CA, US
John Eric Linstadt - Palo Alto CA, US
Venu Madhav Kuchibhotla - Campbell CA, US

Assignee:

RAMBUS INC. - Los Altos CA

International Classification:

G06F 12/00

US Classification:

711103, 711157, 711105, 711E12008

Abstract:

Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path. Moreover, in a second operating mode, the interface circuit communicates with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data.

US Patent:

6775282, Aug 10, 2004

Filed:

Dec 27, 1999

Appl. No.:

09/472858

Inventors:

Ramamohan R. Vakkalagadda - San Jose CA
Venu M. Kuchibhotla - Campbell CA
Michael N. Derr - El Dorado Hills CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 1228

US Classification:

370392, 370438, 710107, 710313

Abstract:

An apparatus includes at least two circuits having interfaces, for transmitting and receiving bus formatted messages and a port coupled to receive messages from the interfaces. The port broadcasts a first received message that is not destined for one of the circuits to the bus. The port blocks broadcast of a second received message that is destined for one of the circuits to the bus.