Van L Snyder

US Patent:

7320100, Jan 15, 2008

Filed:

May 19, 2004

Appl. No.:

10/850057

Inventors:

R. Paul Dixon - Carrollton TX, US
David R. Resnick - Eau Claire WI, US
Gerald A. Schwoerer - Chippewa Falls WI, US
Kelly J. Marquardt - Eau Claire WI, US
Alan M. Grossmeier - Chippewa Falls WI, US
Michael L. Steinberger - Chippewa Falls WI, US
Van L. Snyder - Eau Claire WI, US
Roger A. Bethard - Chippewa Falls WI, US
Michael F. Higgins - Eau Claire WI, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

H03M 13/00

US Classification:

714758, 714718, 714733

Abstract:

A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

US Patent:

7565593, Jul 21, 2009

Filed:

Nov 10, 2006

Appl. No.:

11/558454

Inventors:

R. Paul Dixon - Carrollton TX, US
David R. Resnick - Tucson AZ, US
Van L. Snyder - Eau Claire WI, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

H03M 13/00

US Classification:

714754

Abstract:

A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

US Patent:

7676728, Mar 9, 2010

Filed:

Nov 10, 2006

Appl. No.:

11/558452

Inventors:

David R. Resnick - Tucson AZ, US
Van L. Snyder - Eau Claire WI, US
Michael F. Higgins - Eau Claire WI, US
Alan M. Grossmeier - Chippewa Falls WI, US
Kelly J. Marquardt - Eau Claire WI, US
Gerald A. Schwoerer - Chippewa Falls WI, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

G11C 29/00

US Classification:

714764, 711105, 711154

Abstract:

A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

US Patent:

7826996, Nov 2, 2010

Filed:

Feb 26, 2007

Appl. No.:

11/679175

Inventors:

David R. Resnick - Tucson AZ, US
Gerald A. Schwoerer - Chippewa Falls WI, US
Kelly J. Marquardt - Eau Claire WI, US
Alan M. Grossmeier - Chippewa Falls WI, US
Michael L. Steinberger - Chippewa Falls WI, US
Van L. Snyder - Eau Claire WI, US
Roger A. Bethard - Chippewa Falls WI, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

G01C 31/00
G06F 11/00

US Classification:

702118, 702188, 702189, 702190

Abstract:

A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e. g. , the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

US Patent:

8024638, Sep 20, 2011

Filed:

Nov 10, 2006

Appl. No.:

11/558450

Inventors:

David R. Resnick - Tucson AZ, US
Van L. Snyder - Eau Claire WI, US
Michael F. Higgins - Eau Claire WI, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

H03M 13/00

US Classification:

714758, 36518904

Abstract:

A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

US Patent:

8065573, Nov 22, 2011

Filed:

Nov 19, 2008

Appl. No.:

12/274044

Inventors:

Dennis C. Abts - Eleva WI, US
Gerald A Schwoerer - Chippwa Falls WI, US
Van L. Snyder - Blaine MN, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

G11C 29/00

US Classification:

714723, 714704, 714711, 365200

Abstract:

Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a plurality of counters, the scheduling unit operable to detect a single-bit error in data read from the memory device, and to increment a value in a particular one of the plurality of counters, the particular one of the plurality of counters corresponding to the particular bit in the accessed data which incurred the single-bit error in the read data.

US Patent:

8126674, Feb 28, 2012

Filed:

Aug 27, 2010

Appl. No.:

12/870516

Inventors:

David R. Resnick - Tucson AZ, US
Gerald A. Schwoerer - Chippewa Falls WI, US
Kelly J. Marquardt - Eau Claire WI, US
Alan M. Grossmeier - Colfax WI, US
Michael L. Steinberger - Chippewa Falls WI, US
Van L. Snyder - Eau Claire WI, US
Roger A. Bethard - Chippewa Falls WI, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

G01R 31/14
G01R 31/00

US Classification:

702118, 702119, 702120, 702121

Abstract:

A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e. g. , the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

US Patent:

8245087, Aug 14, 2012

Filed:

Mar 29, 2007

Appl. No.:

11/693572

Inventors:

Dennis C. Abts - Eleva WI, US
Michael Higgins - Eau Claire WI, US
Van L. Snyder - Blaine MN, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

G06F 11/00

US Classification:

714 54

Abstract:

Various embodiments include fault tolerant memory apparatus, methods, and systems, including an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit operable to detect a multi-bit error in data read from the memory device, and to retry the read operation in order to distinguish between an intermittent error and a persistent error.