Tuong P Trieu

US Patent:

6629217, Sep 30, 2003

Filed:

Dec 22, 1999

Appl. No.:

09/469653

Inventors:

Steve J. Clohset - Sacramento CA
Tuong P. Trieu - Folsom CA
Wishwesh Gandhi - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1216

US Classification:

711154, 711163

Abstract:

A method and apparatus for improving read latency for processor to system memory read transactions is disclosed. One embodiment of a system logic device includes logic that assumes a transfer size of a predetermined length. In this manner, the system logic device can issue a read transaction request to system memory as soon as the read request address is delivered by the processor rather than waiting for the processor to deliver information indicating the transfer length. Once the actual transfer length information is delivered from the processor to the system logic device, the system logic device determines whether any of the data returned by the system memory needs to be purged before returning the requested data to the processor.

US Patent:

7180520, Feb 20, 2007

Filed:

Mar 8, 2004

Appl. No.:

10/795939

Inventors:

Sarath Kotamreddy - Chandler AZ, US
Tuong Trieu - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/14
G06F 13/18

US Classification:

345519, 345520, 345535

Abstract:

According to one embodiment a chipset is disclosed. The chipset includes a graphics accelerator, a memory controller and a queue mechanism. The queue mechanism includes a first functional unit block (FUB) coupled to the graphics accelerator, and a second FUB coupled to the memory controller.

US Patent:

7181605, Feb 20, 2007

Filed:

Oct 24, 2003

Appl. No.:

10/693226

Inventors:

Zohar Bogin - Folsom CA, US
Surya Kareenahalli - Folsom CA, US
Anoop Mukker - Folsom CA, US
David Sastry - Folsom CA, US
Tuong Trieu - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/00

US Classification:

713 1, 710267, 711106, 714799

Abstract:

A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.

US Patent:

7230627, Jun 12, 2007

Filed:

Mar 8, 2004

Appl. No.:

10/796686

Inventors:

David E. Freker - Sacramento CA, US
Aditya Sreenivas - El Dorado Hills CA, US
Zohar Bogin - Folsom CA, US
Anoop Mukker - Folsom CA, US
Tuong Trieu - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G09G 5/399
G09G 5/39
G06F 13/00

US Classification:

345540, 345531, 345536, 345537

Abstract:

Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

US Patent:

7612780, Nov 3, 2009

Filed:

Apr 6, 2007

Appl. No.:

11/784342

Inventors:

David E Freker - Sacramento CA, US
Aditya Sreenivas - El Dorado Hills CA, US
Zohar Bogin - Folsom CA, US
Anoop Mukker - Folsom CA, US
Tuong Trieu - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G09G 5/399
G06F 13/00
G09G 5/39

US Classification:

345540, 345531, 345536, 345537

Abstract:

Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

US Patent:

7797492, Sep 14, 2010

Filed:

Feb 20, 2004

Appl. No.:

10/783621

Inventors:

Anoop Mukker - Folsom CA, US
Zohar Bogin - Folsom CA, US
Tuong Trieu - Folsom CA, US
Aditya Navale - El Dorado Hills CA, US

International Classification:

G06F 13/16

US Classification:

711129, 711124

Abstract:

A method and apparatus for dedicating cache entries to certain streams for performance optimization are disclosed. The method according to the present techniques comprises partitioning a cache array into one or more special-purpose entries and one or more general-purpose entries, wherein special-purpose entries are only allocated for one or more streams having a particular stream ID.

US Patent:

20050190193, Sep 1, 2005

Filed:

Mar 1, 2004

Appl. No.:

10/791180

Inventors:

David Freker - Sacramento CA, US
Zohar Bogin - Folsom CA, US
Dour Navneet - Folsom CA, US
Anoop Mukker - Folsom CA, US
Tuong Trieu - Folsom CA, US

International Classification:

G06F013/00
G06F013/372

US Classification:

345534000

Abstract:

An apparatus and a method for adjusting signal timing in a memory interface have been disclosed. One embodiment of the apparatus includes a number of slave delay lock loops (DLLs) in a memory interface to adjust timing between a number of signals to compensate for timing skew, and a number of input/output (I/O) buffers to output the adjusted signals to one or more memory devices coupled to the memory interface. Other embodiments are described and claimed.

US Patent:

20050198459, Sep 8, 2005

Filed:

Mar 4, 2004

Appl. No.:

10/795037

Inventors:

Zohar Bogin - Folsom CA, US
Tuong Trieu - Folsom CA, US
Sarath Kotamreddy - Chandler AZ, US
Jayesh Laddha - Folsom CA, US

International Classification:

G06F012/00

US Classification:

711167000

Abstract:

A method and apparatus for open loop buffer allocation. In one embodiment, the method includes loading requested data within a buffer according to a load rate. Concurrent with the loading of data within the buffer, the data is forwarded from the buffer according to drain rate. In situations where the load rate exceeds the drain rate, read requests may be throttled according to an approximate buffer capacity level to prohibit buffer overflow. In one embodiment, a rate for issuing data requests, for example, to memory, is regulated according to a predetermined buffer accumulation rate. Accordingly, in one embodiment, the open loop allocation scheme reduces latency while enabling sustained read streaming with a minimal size read buffer. Other embodiments are described and claimed.