Tsiu C Chan

US Patent:

6380598, Apr 30, 2002

Filed:

Sep 10, 1999

Appl. No.:

09/393119

Inventors:

Tsiu C. Chan - Carrollton TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

H01L 31062

US Classification:

257390, 257394, 257508

Abstract:

A radiation hardened memory device having static random access memory cells includes active gate isolation structures to prevent leakage currents between active regions formed adjacent to each other on a substrate. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

US Patent:

6381115, Apr 30, 2002

Filed:

Dec 20, 1999

Appl. No.:

09/467617

Inventors:

Tsiu Chiu Chan - Carrollton TX
Elmer Henry Guritz - Flower Mound TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

H02H 504

US Classification:

361125, 361104, 361115, 361124, 327525

Abstract:

A redundant electric fuse circuit is provided that includes a plurality of fuses coupled in series and each having a fuse control device operable for generating a current through each fuse sufficient to blow the fuse. A first fuse control signal is activated to generate a sufficient current through one of the fuses to blow the fuse. A second fuse control signal is activated to generate a sufficient current through the other fuse to blow that fuse. The electric fuse circuit provides redundancy thereby increasing the yield of integrated circuits by reducing the probability that a defective fuse (i. e. , a fuse that reforms after blowing) will cause a fatal defect in the integrated circuit.

US Patent:

RE37769, Jun 25, 2002

Filed:

Sep 29, 1994

Appl. No.:

08/316035

Inventors:

James Brady - Dallas TX
Tsiu Chiu Chan - Carrollton TX
David Scott Culver - The Colony TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

H01L 2120

US Classification:

438385, 438532, 438625, 438647

Abstract:

A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.

US Patent:

6410985, Jun 25, 2002

Filed:

May 2, 2000

Appl. No.:

09/563958

Inventors:

Tsiu C. Chan - Carrollton TX
Anthony M. Chiu - Richardson TX
Gregory C. Smith - Carrolton TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

H01L 2348

US Classification:

257762, 257751, 257753, 257765

Abstract:

Silver interconnects are formed by etching deep grooves into an insulating layer over the contact regions, exposing portions of the contact regions and defining the interconnects. The grooves are etched with a truncated V- or U-shape, wider at the top than at any other vertical location, and have a minimum width of 0. 25 m or less. An optional adhesion layer and a barrier layer are sputtered onto surfaces of the groove, including the sidewalls, followed by sputter deposition of a seed layer. Where aluminum is employed as the seed layer, a zincating process may then be optionally employed to promote adhesion of silver to the seed layer. The groove is then filled with silver by plating in a silver solution, or with silver and copper by plating in a copper solution followed by plating in a silver solution. The filled groove which results does not exhibit voids ordinarily resulting from sputter deposition of metal into such narrow, deep grooves, although seams may be intermittently present in portions of the filled groove where metal plated from the opposing sidewalls did not fuse flawlessly at the point of convergence. Portions of the silver and other layers above the insulating material are then removed by chemical-mechanical polishing, leaving a silver interconnect connected to the exposed portion of the contact region and extending over adjacent insulating regions to another contact region or a bond pad.

US Patent:

6455884, Sep 24, 2002

Filed:

Aug 8, 2000

Appl. No.:

09/634233

Inventors:

Tsiu Chiu Chan - Carrollton TX
Antonio Imbruglia - Catania, IT
Richard Ferrant - Saint Ismier, FR

Assignee:

STMicroelectronics, Inc. - Carrollton TX
STMicroelectronics, S.r.l
STMicroelectronics, S.A.

International Classification:

H01L 27108

US Classification:

257296, 257921, 438238, 438239, 438386, 438399

Abstract:

A radiation hardened memory device includes active gate isolation structures placed in series with conventional oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage potential resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

US Patent:

6486007, Nov 26, 2002

Filed:

Jul 20, 2001

Appl. No.:

09/910396

Inventors:

Tsiu Chiu Chan - Carrollton TX
Mehdi Zamanian - Carrollton TX
David Charles McClure - Carrollton TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

H01L 21335

US Classification:

438142, 438199, 438229, 438305, 365154, 365156, 257 59, 257 66

Abstract:

A method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.

US Patent:

6518620, Feb 11, 2003

Filed:

Nov 18, 1998

Appl. No.:

09/195089

Inventors:

Tsiu Chiu Chan - Carrollton TX
Pervez H. Sagarwala - Grand Prairie TX
Loi Nguyen - Carrollton TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

H01L 29788

US Classification:

257321, 438263, 438594

Abstract:

A memory cell for an EEPROM memory is fabricated to provide increased oxide thickness at the edge of the tunnel oxide and under the edges of the polysilicon capacitor plate in order to improve the dielectric integrity of the capacitor structure. In one embodiment using a silicided polysilicon process, the oxide is made thicker at the edge of the tunnel oxide by reoxidizing the silicon at the corner of the polysilicon capacitor plate and the underlying substrate surface by exposing the device to a short duration oxidation step after having deposited a 200 to 500 thick porous oxide over the device to protect the silicide from excessive exposure to the oxidizing ambient. In another embodiment the tunnel oxide is grown in a window in the gate oxide layer, which is about four times thicker than the tunnel oxide, so that the gate oxide completely surrounds the tunnel oxide, and the polysilicon capacitor plate extends beyond the edge of the tunnel oxide terminating at a point above the gate oxide.

US Patent:

6580133, Jun 17, 2003

Filed:

Aug 7, 2001

Appl. No.:

09/923746

Inventors:

Tsiu C. Chan - Carrollton TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

H01L 2976

US Classification:

257382, 257754, 257760

Abstract:

A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a conductive structure over a portion of a first body. A thin dielectric layer is formed at least partially over the conductive structure. A thick film, having a high etch selectivity to the thin dielectric layer, is formed over the dielectric layer. The thick film is patterned and etched to form a stack substantially over the conductive structure. An insulation layer is formed over the thin dielectric layer and the stack wherein the stack has a relatively high etch selectivity to the insulation layer. The insulation layer is etched back to expose an upper surface of the stack. The stack is then etched to form an opening in the insulation layer exposing the thin dielectric layer which acts as an etch stop during the stack etch process.